Tool/software:
Hi team,
My customer found a plateau in the VCE during its descending process while conducting a double-pulse test. Is there any way to optimize it?
Regards,
Sveinn
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Tool/software:
Hi team,
My customer found a plateau in the VCE during its descending process while conducting a double-pulse test. Is there any way to optimize it?
Regards,
Sveinn
Hi Sveinn,
What is the input capacitance of the module? Looks like it has high capacitance, We need to increase the drive strength to enable faster Vce transition. It can be done by,
Thanks
Sasi
Hi Sasi,
Thanks for your help.
I have another question.
Is the 400mA of STO a constant current source? What is its internal structure?
Regards,
Sveinn
Hi Sveinn,
Due to the holiday in the US on 20th Jan 2024, many of the device experts are currently out of the office.
I can help answer this in the meanwhile. Yes, 400mA is a constant current source.
Thanks,
Pratik
Thanks Pratik for your quick support.
Hi Sveinn
There is a internal NMOS FET pulls the OUTL to VEE with around 400mA drive strength based on the internal resistance on the gate. It is not a current source.
Thanks
Sasi
Hi Sasi,
based on the internal resistance on the gate
How to understand 'Based on the internal resistance on the gate' Do you mean Rg_int or Rol or others?
If it is Rol, what is the value of Rol?
Can the driving resistor on OUTL affect the STO current? If yes, is there a rough formula to calculate the current?
For example,
As we communicated in the email, our test conditions do not indicate the voltage difference between VOUTL and VEE.
Can you explain how the current of around 400mA is determined?
Regards,
Sveinn
Hi Sveinn,
I meant internal resistance of the pull down FET. It is ~20V/400mA = 50 ohms (during linear mode of the FET operation). 20V is at OUTL wrt to VEE
If you consider voltage at GATE not OUTL, then need to consider the external gate resistance as well.
Thanks
Sasi