This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

UCC21540: Noise coupling when driving Half-bridge, SPWM gate signal for inductive load

Part Number: UCC21540
Other Parts Discussed in Thread: ALLIGATOR

Tool/software:

A half-bridge circuit has been designed to drive an inductive load, with a sinusoidal pulse-width modulation (SPWM) signal controlling the switching. However, during operation, significant noise coupling into the low-voltage section has been observed when the half-bridge switches.

The circuit uses the UCC21540AQDWKRQ1, an isolated gate driver, for driving the MOSFETs. The SPWM signal is generated onboard by comparing a triangular waveform with a sinusoidal reference. Given the isolation provided by the gate driver, any disturbances on the high-side of the gate drive should ideally not affect the low-voltage section.

Despite this, common-mode (CM) noise has been detected in the low-voltage power rails (5V and 12V). The noise exhibits a frequency of greater than 45 MHz and an amplitude of approximately 3-4 V peak-to-peak. The high-side of the gate driver is powered externally, yet the issue persists.

For this test, the DC-link voltage was set to 24 VDC. The output of the half-bridge is filtered using an LC filter, resulting in the expected output: a 12 VRMS AC signal.

Please see the attached schematic for reference

The high-side MOSFET in the half-bridge is driven using a bootstrap circuit. When the gate voltage is probed with Q18 connected and Q17 not connected (NC), the observed behavior is as shown below. Could you suggest potential reasons for this behavior? Your insights would be greatly appreciated.

  • Hi Althaf,

    Thank you for reaching out and providing all of these details.

    3-4Vpkpk on the low voltage rails seems concerning. What probe are you using for this measurement? Is this measured using an alligator clip probe? This could potentially be noise picked up by the probe's ground loop.

    Some additional questions to help me better understand this:

    • Just to confirm, is the secondary side supply an isolated supply?
    • Do you have any zoomed in captures of the abnormal output waveform?
    • What does the high-side output waveform look when both Q17 and Q18 are disconnected?

    Looking forward to hearing back.

    Regards,

    Hiroki

  • Hi Hiroki,

    I have ruled out probing issues and confirmed that the high-side and low-side supplies of the gate driver are properly isolated. If Q17 and Q18 are not populated, we only observe the gate signal of the low-side MOSFET (Q18) since the bootstrap path required to power the high-side MOSFET remains incomplete.

    Given this, the issue I am experiencing on the board is likely related to the PCB layout.

    Please find the attachments,

    The above attached image is the actual dc link voltage across the half-bridge!

  • Hi Althaf,

    Great to hear that there is proper isolation in the system.

    What does the high-side output waveform look when both Q17 and Q18 are disconnected?

    Sorry for the confusion on this request. I wanted to see the gate driver switching behavior with no load connected since the waveform screenshot of the output seemed very abnormal.

    Is this occurring on more than 1 gate driver unit? I would recommend you to try an ABA swap test to see if the issue is specific to the board or to the device.

    I am also able to review the layout in case there are any possible concerns there (either by email or private message if preferred).

    Regards,

    Hiroki

  • Hi Hiroki,

    The issue is not related to faulty components, as I have tested multiple boards and performed an ABA swap, yet the problem persists. I strongly suspect that this is a layout-related issue.

    If you can share your email, we can discuss the layout in detail. I believe the high-side MOSFET gate drive issue might be linked to the bootstrap design. However, I have followed the guidelines outlined in TI’s application note.

    Looking forward to your insights.

    -Althaf

  • Hi Althaf,

    Thank you for that clarification!

    I have sent you a friend request to share emails.

    Closing this thread to continue discussion through email.

    Regards,

    Hiroki