LM5060-Q1: LM5060 nPGD state when EN=0

Hi Stas,

It is not expected. Can you probe GATE, Vout, input current and nPGD in oscilloscope 

Also check by shorting  R105

Best Regards,

Rakesh

I see this in datasheet. Basically when EN low output state is not defined. I just expected it to be high in my logic.

Hi Rakesh!

Thanks for advice!

What I did: I removed R19 (disconnect nPGD from system) and still had 1.6V in system.

That was strange. This line was connected only to:

 - R109 100K pull-up (33uA)

- C62 100nF capacitor to GND

- 2x LM74930 EN ideal diode controller (typ 55 nA, max 200nA)

- 1x SN74LXC8T245RHLR level shifter to drive LEDs (2 uA max leakage)

Total max leakage of 2.5uA against pull-up 33 uA should not eat half voltage, only 10%.

I replaced  R109 with 2K and put back R19 - now I have high voltage as I desired in logic design.

I checked with oscilloscope nPGD output - stable.

Looks like I have some major leakage

Update: I have fault signal that goes to LED driver and NAND gate, also pulled up 100K and 1.6V.

Looks like SN74LXC8T245RHLR is the leakage guy (like 30uA input leakage) or 100uF capacitor

Can you please share test results of EN, GATE, Vout, input current and nPGD from oscilloscope

Best Regards,

Rakesh

Hi Rakesh!

I bypassed nPGD, anyway I need another signal as control logic.

But I have another problem - LM5060 is not working anyway.

I made R111 (lower resistor for UVLO as 20KOhm with 100-20Kohm ratio) to make sure UVLO is not a problem

I have VCHRG shorted to INH (VIN to EN) and gte is not open.

I see VSENSE = VEN   is 24V, VOUT=0V, VUVLO = 4V, VGATE = 0V with oscilloscope it is stable.

What may be wrong?

Hi Stas,

Can you check the timer to see if the device is entering into any fault ? 

What is the load during this test ?

Please share some waveforms

Best Regards,

Rakesh

Hi Rakesh!

Sorry for delay, I was sick.

I figured out the problem: D12 zener diode befre VIN on my board. I found out when I have 20V I have Vin 8V.

I removed it and all started to work.