This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

UCC289x - what CS parts should be near the IC?

I'm designing a high-power UCC2893-based supply with a CT for sensing current. In my system, the PWM IC isn't right next to the CT because of large components and the heatsink.

What parts should go near the CT and what parts should go near the IC? My current sense scheme looks like page 27 of the datasheet (http://www.ti.com/lit/ds/symlink/ucc2891.pdf), with the CT on the drain of the main FET. I'll use those ref des as an example. In a previous design using the same IC and CT, I placed R7 near the CT and everything else near the IC. I ran the traces from R7 as a diff pair to D1 and the plane of the IC. That worked OK, but waveform fidelity wasn't exemplary.

In my current design the CT is ~2" from the IC. Should I repeat the same component arrangement as above? Put everything except for R6 and C5 near the CT, with the RC filter near the IC?

Of course I looked at UCC2891EVM / HPA034. It doesn't exactly have this issue because the CT and IC are so close together there's just enough room for the parts.

  • Evan,

    The objective is to keep noise out of the current signal. To that end i would not have positioned the Ct in series with the drain. This will add an interwinding capacitive coupling noise factor to the noise. Once Q2 shutsoff and the voltage at the drain of Q2 transitions to the reset levels the only current flow through the primary is the magnetizing current and that reverses direction only during the last half of the off time and will be small compared to the forward current with the load. All you need it to do is reset the current transformer.    

    As far as positioningis concerned it depends on what noise is directed into the CS pin. That should be kept as clean as possible. you have to look at capacitive and inductive coupling to the leads in your layout.. keep the two traces to the CT from the chip (ground and the CS lead) right nest to each other to minimize inductive pickup and equalize any capacitive pick up.

    You might wwant to split C8 into two caps. One next to R9 at the transformer and one between R6 and ground at the IC.

    You might find the attached informative.

    http://www.eetimes.com/design/power-management-design/4012207/Keep-The-Ramp-right

     www.bodospower.com/pe/restricted/downloads/bp_2007_09.pdf   pages 46 to 49

    Regards,

    John