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UCC28070A: Modify controller feedback to achieve a lagging PF

Devin Watson
Prodigy 10 points
Part Number: UCC28070A

Tool/software:

Currently using the UCC28070A as my controller for an interleaved boost PFC. My program requires a lagging PF of .8 to 1 above 100VAs, and our current solution is adding inductors from line to line to pull the lagging current. Is it possible to add a capacitor or other circuitry into the control loop of the UCC28070A  to get a lagging current from the PFC and get rid of the inductors all together.

  • 0
    TI__Mastermind 40580 points

    Hello Devin, 

    Generally the PFC current loop is always following behind the AC input sine voltage, so the PFC current is naturally lagging, however, only by a tiny amount. 
    Usually the EMI filter X-caps add more than enough leading reactive current to swamp out any of the natural lag.

    Two places where a capacitor may add lag are: at the VINAC input and at the IMO output.  Both have issues. 

    Adding too much capacitance to the VINAC input will filter out the zero-crossing "details" and that will prevent the quantized feed-forward block from working. 
    The zero-crossings will be lost and the I-loop gain stuck at the level where the last detectable zero-crossing occurred. 
    I recommend against lagging at the VINAC input. 

    Adding a capacitor on the IMO output will delay the rise and fall of the IMO rectified-sine signal (which normally would follow the VINAC signal).  
    Since it is a current source, the rising edge delay can be "predicted" based on the current split between the cap and the IMO resistor. 
    But since IMO is not a current sink, the falling edge delay is a more complicated function of the IMO resistance, assuming that Iimo falls faster than Vimo. 
    It will not be simply a time-delay of the sine shape, but will have some additional distortion components. 

    And there is still the question of how much lag can be added that way, if it is able to overcome the phase lead of the X-caps, which is worst-case at high line, 63Hz. 
    Minimizing or eliminating the X-caps (if that is possible) will help. 

    A last-minute thought: it may be possible to design a literal time-delay circuit that takes the output of the VINAC resistor-divider string and time-shifts that voltage before feeding the VINAC input.  Aside from the complication of this, there may be additional distortion when the IMO output (following the time-shifted VINAC) is driving non-zero current while the voltage is at the zero-crossing, and then when the voltage climbs out of the zero-crossing even while the IMO signal is falling toward its own zero.  

    Other than that, I know of no way to "program in" a phase lag of the AC current. 
    At least maybe a limited cap on IMO may help reduce the amount of inductance you'll need to add to the lines. 

    Regards,

    Ulrich