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Original question:

[FAQ] LM74930-Q1: What is the function of diode on VS pin

LM74930-Q1: Questions on OVCLAMP, output capacitance and PWM

Harald Trübswetter
Prodigy 10 points
Part Number: LM74930-Q1
Other Parts Discussed in Thread: LM74930, , LM74502H

Tool/software:

Hello,

I have some questions on the LM74930.

It is not clearly in datasheet how to handle the OVCLAMP Signal.
Can you check, if my understanding is OK?

- OVCLAMP pulled to GND (OV connected to Input) => no overvoltage clamping => output switches off during overvoltage

- OVCLAMP connected to OV pin => in this case the output voltage is limited at overvoltage => OV voltage divider must be connected to output

- OVCLAMP connected to OV pin and voltage divider connected to input => output switches off during overvoltage (makes no sense due to clamp-function)

In the calculation sheet a "Required Maximum allowed Inrush Current" should be specified.
Our application has a resistive load current of up to 35A. Is this (or a value above) also the Inrush current for the calculation?


The Turn-on Gate currents are very low (55µA). I'm not sure, if this leads to a problem due to slowly switching MOSFETs.
The calculation don't checks the Gate charge of the MOSFETs.
We also want to use the Chip with a slow PWM application (about 1Hz or up to 10Hz).
Would this be possible via the Enable pin?

Can Simulation be done with the TI PSPICE simulator? Actually I'm not able to download the SW.

Best regards
Harald

  • 0
    TI__Mastermind 33835 points

    Hi Harald,

    LM74930-Q1 spice model is not compatible with Pspice for TI yet. Please use ORcad Pspice to simulate.

    When OV_CLAMP is connected to GND, OVCLAMP does not work with TMR, it works independently.

    In the first waveform, OV is referred to VOUT. Since OVCLAMP is Grounded, clamp duration is indefinite.

    In the second waveform, OV is referred to VOUT and OVCLAMP is connected to OV. Hence clamping happens for set duration.

    In the third waveform, OV is simply referred to VIN, Hence Cutoff. OV_CLAMP is grounded.

    HGATE drive strength is kept low intentionally to keep the inrush current in limit for slow turn-on. Inrush current in calculation tool is just the amount of current flowing into bulk capacitors. Any resistive load will be added on top of Inrush. Although it is important to know that MOSFET will be under very high stress during startup if bulk capacitors and resistive load both are sinking current.

    1-10Hz PWM should be fine although controller takes time to turn-on as charge pump needs to build up with every EN cycle. You can try to PWM with UV/OV pin.

    Regards,

    Shiven Dhir

  • 0 in reply to Shiven Dhir
    Prodigy 10 points

    Hi Shiven,

    thank you for your answer. OK, now it is clear how to handle the OVCLAMP. I overlooked it at datasheet...

    Is there a difference if we do PWM an OV or UV pin? UV can probably be simpler to manipulate by switching to GND. Additional we will get a fault signal.
    If we do PWM over Enable, what are the disadvantages?
    There will be a startup delay of 270µs and probably some time for charging the bootstrap cap. Due to large gate capacitance (2x 14nF at HGATE) we will use 1µF at CAP. But I don't think that the cap will be discharged during the Off-phase of the PWM or how will it react at lowphase?

    An other topic is the low H-gate charging current of 55µA. The simulation (charging the Gate with 55µA) shows me a plateau time of 1,5ms. If I adapt this in the calculation sheet to 22V/ms it looks OK at SOA evaluation, also at worst-worst case the margin is 1.15. Can I trust them or should I check it with the MOSFET supplier? 1,5ms is not a typical small time.

    There is also a trick necessary at Step 4 calculation in the sheet. The calculation don't checks that we use two MOSFETs parallel and therefore the load current is divided into this two MOSETs. So I doubled the load resistor value.

    I got the TI PSPICE simulator and it looks like the Orcad. Is it worth to try it with this simulator?

    Regards, Harald

  • 0 in reply to Harald Trübswetter
    TI__Mastermind 33835 points

    Hi Harald,

    EN PWM will have larger delay. Bootstrap capacitor does not have an active pull down and it will only discharge due to leakages.

    1.14 may be low margin.  You can try increasing Cdv_dt further.

    Also, I agree that you are using 2xparallel FETs but during startup we assume that entire stress is on one single FET. For steady state we divide the stress equally. Hence, please scale the startup considering that you only have 1xFET.

    Regards,

    Shiven Dhir

  • 0 in reply to Shiven Dhir
    Prodigy 10 points

    Hi Shiven,

    could you explain how can I change Cdv_dt (in practice, not in Excel)? We have no additional capacitor connected to the HGATE and an additional cap. makes no sense.

    I assume, that the calculation don't considers the Gate Charge of the MOSFET, which I don't understand. As I described, one MOSFET IPTC020N13NM6 has 14nF total Gate charge.

    Or how can we speed up the switching time to optimise SOA margin? Additional Gate driver?

    I will check other MOSFETs with lower Gate charge, but this will lead to more RDSon and therefore to more powerloss.

    Regards, Harald

  • 0 in reply to Harald Trübswetter
    TI__Mastermind 33835 points

    Hi Harald,

    I am referring to the RC as shown in datasheet which helps control the slew rate of VOUT.

    Regards,

    Shiven Dhir

  • 0 in reply to Shiven Dhir
    Prodigy 10 points

    Hi Shiven,

    Probably I found my mistake in the calc-sheet.

    You can also choose "No" at Soft-Start control. But is it correct, that only Crss is relevant for the calculation?
    In this case all looks fine.

    Regards, Harald

  • 0 in reply to Harald Trübswetter
    TI__Mastermind 33835 points

    Hi Harald,

    With No Cdvdt cap, the inrush current maybe high. It is a system level requirement, and you can choose to not use that capacitor. 

    Yes, Crss is the only relevant spec. when Cdvdt is not used.

    Regards,

    Shiven Dhir

  • 0 in reply to Shiven Dhir
    Prodigy 10 points

    Hi Shiven,

    I'm not sure, if Crss is the correct value for the calculation.

    If I use Crss, which is about 80pF with our MOSFETs, I get the SOA limit in the calc sheet in the range of the 10µs power limit.
    As I told you yesterday, wenn I simulate the switch on of the MOSFETs with 55µA HGATE current, the switching time is around 1ms.

    Could you check, if the calculation with Crss is correct or what is the fault in my simulation?

    In the calc. I changed the ambient temp. to 25°C, so therefore there is no temperature correction and SOA can be compared to datasheet.

    Regards, Harald

  • 0 in reply to Harald Trübswetter
    TI__Mastermind 33835 points

    Hi Herald,

    Crss is Cgd value of MOSFET which defines the miller plateu region of the FET.

    When Cvd_dt is not used, only capacitance that will influence the miller's region is Crss.

    Crss does not define the total startup time of the FET, that is still decided by Ciss dominently.

    Because of this you see 1ms startup time.

    Regards,

    Shiven Dhir

  • 0 in reply to Shiven Dhir
    Prodigy 10 points

    Hi Shiven,

    no I don't see 1ms startup time. What I see is about 1ms switching time (the time interval at miller plateau). And additional 1,5ms startup delay time before.

    The Gate charge at threshold is about 22nC per MOSFET at 30V. => 44nC / 55µA = 0,8ms

    That's what me makes worry.

    We will try it in a few weeks with HW, but it would be good, if you can check the calc. Tool.

    Regards, Harald

  • 0 in reply to Harald Trübswetter
    TI__Mastermind 33835 points

    Hi Harald,

    Without any dv_dt capacitor, the miller plateau region will be small.

    I am unsure why simulation shows that long.

    Regards,

    Shiven Dhir 

  • 0 in reply to Shiven Dhir
    Prodigy 10 points

    Hi Shiven,

    the reason is the very low gate driver current of 55µA.

    Regards, Harald

  • 0 in reply to Harald Trübswetter
    TI__Mastermind 33835 points

    Hi Harald,

    Low gate drive of 55uA is kept on purpose to limit inrush current.

    If you want fast driver and inrush current isnt an issue, you can consider using LM74502H and can PWM with OV pin.

    Regards,

    Shiven Dhir

  • 0 in reply to Shiven Dhir
    Prodigy 10 points

    Hi Shiven,

    LM74502H is not useful.

    We need an overvoltage protection for voltages up to 135V (TVS will limit the original pulse auf 250V). Additional there is a long 100V Surge pulse, which the TVS can't limit.
    We have load currents up to 35A. We don't want an additional switch for the slow PWM with some Hz (because of power dissipation and PCB space).
    We need also a protection against reverse polarity.
    Current measurement and short circuit protection is also necessary.

    The LM74930 meets all this requirements.

    The only thing is the slowly turn on time because of the 55µA Gate current.

    From functional side 1ms turn-on time (plateau) is OK. And also some delay.

    It is only the question, is it also OK for the MOSFET..? Can we trust the SOA calculation in the Excel?

    Regards, Harald

  • +1 in reply to Harald Trübswetter
    TI__Mastermind 33835 points

    Hi Harald,

    SOA calculation tool can be trusted only to some extent. It given an idea on how bad the startup scaling is. SOA startup margin the higher the better. If SOA tool says that margin is low, the hardware will fail surely but if it says the margin is enough, there might be some corner failure case. It is good to test everything on hardware as well.

    To conclude; SOA tool just gives an idea.

    Regards,

    Shiven Dhir