Tool/software:
If the MCU and the I2C pullups are powered on before the BQ, everything works just fine.
But in our current design, normally the BQ is woken first and the voltage domain that powers the MCU and I2C pullups is only supplied with a ~20ms delay, in the meantime the bus lines don't have pullups.
Apparently this causes the I2C interface of the BQ to lock up because it will never again ACK any command but I can see that REG1V8 and REG1(3V3) are online so the BQ must be active.
Is this theory plausible and if so, what are the exact conditions for that to happen?
For the next PCB revision we intend to change how the pullups are supplied but for the current revision we still need to get it working somehow.
My idea of a workaround was to reset the BQ as soon as the MCU boots by setting the RST_SHUT pin for 10ms.
That does resolve the I2C issue but creates a new problem, the accumulated charge is then reset to some garbage value.
So I try to send it a RESET_PASSQ subcommand as well but that is without effect unless I insert a 300ms delay between RST_SHUT going low again an the subcommand being sent.
What is going on here, why is this delay needed and where is it documented?
Also:
Why does the OTP_WR_CHECK subcommand take up to 200ms to execute?
If I send the device a RESET subcommand, I need to wait 20ms before the next command is accepted, why is this not documented?
If I try to read from 0x0084, it never seems to complete, 0x3e and 0x3f always returning 0xff, why is that?
And why is a "CRC" appended to every byte? That defies the logic of a CRC, why not implement it properly and get rid of the checksum at 0x60 instead?
So far, implementing the driver for that IC has been a complete frustration..
BR