Tool/software:
I was sitting through a presentation about using a 2-port probe to measure output impedance versus frequency, and there was an example of the TPSM843B22 which had a high impedance peak at 1.44MHz.
Is this EVM design stable?
Where does this impedance peak come from?
Is there any way to improve it?
Is there any way to avoid this during design?
A great question. Before we go into the details of the TPSM843B22, let's talk about what a 2-port probe is and how it's measuring output impedance.
A 2-port probe is a specialized measurement tool that has a head with 4 closely spaced pins in 2-pairs - 1a & 1b and 2a & 2b. One pin from each pair is connected to each of the two "ports" - Port A and Port B
The probe allows one port (Port A, pins 1a and 2a) to generate a forcing condition, while the second port, (Port B, pins 1b and 2b) senses the results of that forcing condition with as little mutual resistance and inductance as possible. This allows kelvin sensing of the results of that forcing condition.
For an impedance measurement, one of the ports drives a voltage between one pin from each pair (1a and 2a for example) through a known resistance - typically 50-500Ω, while the other port measures the differential voltage between other pin from each pair (1b and 2b, for example). By calculating the current forced through the known resistance and comparing it to the measured voltage, the ΔVac / ΔIac - or dynamic impedance, can be calculated.
Due to the very low levels of current and voltage used, the probes and test equipment is typically calibrated before each test against an Open Circuit, A Short Circuit, and a Known precision resistance on the order of the measurement to be taken.
For example, driving a 1Vac signal across a 50Ω impedance creates a current of 20mA. For a measurement of 1mΩ, as seen above from 1Hz to 3kHz, the measuring port is measuring just 20μVac.
When the impedance curve reports an impedance of 3mΩ (200kHz above) that means that a 1Aac load at 200kHz will produce a 3mVac ripple on the output @ 200kHz
Is this EVM design stable?
Yes. The EVM design is stable. The EVM's output wont oscillate and it will return to regulate cleanly after a single impulse transient.
The 20A load-step transient response and Gain-Phase BODE plot showing 100kHz of bandwidth and 50 degrees of phase margin are shown in Figure 3-8 and 3-9 of the EVM User's Guide - https://www.ti.com/lit/ug/sluuck9/sluuck9.pdf#page=12
The impedance peak isn't a stability concern. However, if there is loading current on the output at 1.44MHz, there may be higher output ripple or noise at 1.44MHz than at other frequencies due to the higher impedance at that frequency.
As an example, if we applied a 1A load pulse for 347ns (half-cycle of 1.44MHz) we would expect to see a 7mV "spike" on the output due to the 7mΩ impedance measured at 1.44MHz.
This is above the switching frequency of the TPSM843B22, which was operating at 1MHz, and this peak is coming from the Output Capacitors, not the TPSM843B22 module itself.
Where does this impedance peak come from?
As I just said, this is coming from the output capacitors, not the module.
From the Users Guide Schematic - www.ti.com/.../sluuck9.pdf
We can see that the output is made up of 4x 100μF + 2x 10μF + 2x 1.0μF + 2x 0.1μF
The 100μF capacitors have a self-resonant frequency at 500kHz, creating the first "trough" or "canyon" in the impedance curve, with the 4 in parallel driving the impedance down to about 1mΩ
The 10μF capacitors have a self-resonant frequency of 2MHz, driving the output impedance down to about 1.8mΩ at that frequency
But the spacing between the self-resonant frequencies results in a peak impedance at the geometric mean between them - which we are measuring at 7mΩ at 1.44MHz.
What is happening is the parasitic inductances of the capacitors (ESL) and the two capacitors are trading energy back and forth at 1.44MHz. It's called "Inter-capacitance resonance" and it will cause a "peak" in the spectrum of the output ripple at 1.44MHz when the output is loaded with "random" load changes.
Is there any way to improve it?
Absolutely!
If we added a capacitor with it's own self-resonance frequency at (or very close) to 1.44MHz, it would reduce the impedance at 1.44MHz and conduct any resonant energy to ground. If we review capacitors, we'll find a 47μF capacitor and a 22μF capacitor will have self-resonant frequencies either side of 1.44MHz. If we could find one, a 33μF capacitor would likely have a resonance right at 1.44MHz, being about 1/3 of 100μF and 3x the 10μF.
So, if we change one of the 100μF capacitors to a 47μF capacitor and one of the 10μF capacitors to a 22μF capacitor, we'll reduce the total capacitance by 85μF while we'll significantly improve the impedance between 500kHz and 2MHz.
Is there any way to avoid this during design?
As a general rule, it's best to avoid paralleling larger capacitors in 10:1 ratios, like a 100μF and 10μF or 10μF and 1.0μF.
In fact, if we look at the impedance curve, we can see a second inter-capacitance resonance between the 10μF and the 1.0μF capacitors up at 5MHz and 5mΩ (Highlighted in green below)
The ideal spacing for these capacitors is about 1/π - but most capacitor vendors don't make these larger ceramic capacitors in 33μF or 3.3μF so we generally have to settle for about 2.2:1 (10 to 4.7 or 2.2 to 1.0) so we end up with a progression of 100μF 47μF 22μF 10μF 4.7μF 2.2μF and 1.0μF
How far down do you need to go?
Generally by 0.1μF, the ESR of the capacitors has risen high-enough that the capacitors are self-damping and we don't see inter-capacitance resonance. For example, the 0.1μF capacitor used in the TPSM843B22EVM has an ESR of 30mΩ and a self-resonant frequency of 36MHz. Now, if you look at the impedance curve closely at 30MHz, you can see a very small "hitch" at 30mΩ and 30MHz, but not enough to create added noise at that frequency.
