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LM74930-Q1: LM74930-Q1: Polarity inversion protection + battery charger

Part Number: LM74930-Q1

Tool/software:

Hi guys,

Hope you are doing well.

I am working on a battery (INR18650) protection circuit against polarity inversion & overcurrent (possibliy voltages min/max).

In a previous topic, the following schematics was suggested to me in order to allow bidirectional charging / discharging (battery can be charged over USB).

LM74930-Q1: Polarity inversion protection + battery charger : https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1452194/lm74930-q1-polarity-inversion-protection-battery-charger

I implemented it but I am experiencing some issues : NMOS does not activates themselves and so the power output never come ; 

- Vin is supposed to vary from 3 to 4.2V (battery cell)

- when Vin < 5V, Vout = 0V

- when Vin > 5.4V, Vout have a strange behaviour (only since I added the diode drawn, before, nothing happened whatever the voltage is)

- I tried to remove OV (tied to GND then) / UVLO (tied to VS then) and ILIM (tied to GND then)

- It changed nothing.

Any Ideas ?

Nb : MOSFETS are Toshiba TPN1R603PL,L1Q

Below are for Vin > 5.5V : VS (left), Va (mid), Vout (right) 

       

Best 

Jimmy

  • Hi Jimmy,

    I see that OUT/A to VS diode is missing in your schematic. Can you add it and test again?

    Regards,

    Shiven Dhir

  • Dear Shiven, 

    Hope you are doing well and thanks again for your support !

    I tried placing a diode as mentioned but it changed nothing infortunately.

    As an example, With Vbat = 4.4V (stabilized power supply), Vs = 3.1V, Vout = 0V, Dgate and Hgate = 0V.

    I even tried to remove "optional features" Ilim, UVLO, on a second board (with respect to the datasheet but nothing changed.

    Riscp = 0R

    Rest = 49.9R

    Rsense = 0.001R

    EN / MODE connected to Vbat

    on first board, OV not used, UVLO = 0.6V when Vbat = 3V, 100K ; 25k , Ilim = 20K -> target = 30A

    on both board, Rmon = 3.6K -> full load for 30A 

    Any ideas on what is happening ?

    ---

    I made additionnal testings : I had the feeling that Vs voltage value was a thing, so I shunted R1 (Rset).

    Now the module is working I have Vbat = Vout with some specific behavior : 

    - When Vbat is changing (let's say form 5V to 3V), everything is linear.

    - If Vbat is going below 3V, then the Vbat << Vin (around 1.8V for 3.3V or 2V for 4V, see picture) until Vbat reach 4.2V (or higher), then everything is going back normal

    this has been tested on a bord with UVLO and ILIM used (so 3V is supposed to be the threshold I set up)

    Finally, if the power supply is inverted (RPP): 

    - the system is going back linear if Vbat >= 4.2V

    - is having the same not linear behavior if Vin < 4.2V (this is solved when Vbat cross again the 4.2V limit

    Hope this can give you some additional informations..

    Best

    Jimmy

    Best

    Jimmy

  • Hi Jimmy,

    I suspected R111 to be an issue which is not letting VS rise at low voltages. That resistor is added to fight some transients, and I think they are not expected in your system. Hence you can choose to remove it or lower down its value to something like 100 and test again.

    Can you help me understand what does linear mean?

    Regards,

    Shiven Dhir

  • Hi Shiven,

    by linear i mean (but you are right, it is not the right term) having Vbat = Vout

    I tried with 100R. It work the same except when i draw current -> it make the situation a bit better, thanks

    I have a second issue : the max current is supposed to be 30 Amps according to the settings (and without errors) but when the consumption goes higher than 5 Amps (average), the system cuts.

    I tried the short Rilim to remove the overcurrent protection. 

    I got some fluctuation but nothing going under 3V 

    Any ideas ?

    best

    ---

    Left = Vo ; Right is Vnom (3Amps)

       

       

  • Hi Jimmy,

    I hope UVLO is not getting triggered as it set to 3.01V(typ).

    Can you disable UVLO and test again? You can remove R117.

    Regards,

    Shiven Dhir