TPS62873-Q1: schematic review

Hi Jeff,

Please find review for shared schematic as design follows reference design and my apology for late reply,

VDD_CORE_0V8:

• It is good to place 2 x 0.47uF on input to reduce the high freq noise and can be place close to device. 
• There is ~1mF capacitor bank close to SoC. We can reduce local capacitor (close to IC)  to 1 x47uF

VDD_CPU_AVS:

• It is good to place 2 x 0.47uF on input to reduce the high freq noise and can be place close to device. 
• Large capacitor bank close to SoC. We can reduce local capacitor (close to IC)  to 1 x47uF

Please kindly share layout files once design is done.

Best regards,

Tanvee

Hi Jeff,

Let me jump-in to the discussion as Tanvee is out office.

The 2x 0.47uF output capacitors are placed to suppress the high frequency voltage spikes typically generated by the SW node. But in other applications, the low capacitance are placed closed to the system load which filters all high frequency noise from the buck converter to the point-of-load. So, there are different design approach to minimize the noise in the system. It's either filter immediately from the source or in the load side.

I hope I was able to address your queries.

Best regards,

Excel