Tool/software:
Hi team,
We use UCD9081 to control the power-on timing of the CX8 chip as shown in the figure.
When powered on, P3V3--->P1V8--->VDD..., when powered off, VDD, VDDP, DVDD--->P1V2-->P3V3--->P1V8, the power-off timing does not follow the timing that the logic that the last power on is powered off first, and the first power on is powered off last.
According to this design requirement, can UCD9081 meet the requirements of power-on and power-off timing?
What's more,
How to deal with the unused channel? Floating/pull-high/pull-down? and Ignore?
Thanks a lot, and looking forward to your reply.
BR,
Matt.
