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UCC21750: Gate driver stops working above 750V DC

Bernhard Baier
Prodigy 10 points
Part Number: UCC21750
Other Parts Discussed in Thread: UCC21710

Tool/software:

Hi there,

we designed a 3-phased inverter using a SiC MOSFET and six UCC21750 drivers. We use a half-bridge driver with two UCC21750 per PCB. The simplified design is shown below.


The inverter works well up to ~750V DC. Above 750V DC we see that the bottom FET is no longer turned on reliably. For the first example, we measured:

CH1: current (no load)
CH2: IN-
CH3: Gate
CH4: IN+



The example shows the Gate being turned on in the beginning and then in the second clockcycle the Gate is initially turned on, then falls off, rises again and then stays low.
There is quite some noise on the signals. We don't have a opto coupled isolated probes so it might be a measurement problem... Here is a comparison of a working turn on and a non working:

Since the noise on the working turn on is quite similar to the non-working one (and the difference of In+ - In- is not affected by the oscillation) we suspected the DESAT (although we did not get a Fault from the driver).

I switched to non isolated probes measuring only the high voltage side:
CH1: current
CH2: VDD
CH3: Gate
CH4: DESAT

With a valid turn on we get ~5.5V at the DESAT pin which is well below the 9.15V threshold. The big oscillations are gone with the non-isolated probes and the signals seem to be fine. Still we will also get non working turn ons, even with no probes connected.

We went on measuring the RDY pin, changing to isolated probes again:
CH1: RDY
CH2: IN+
CH3: Gate
CH4: IN-

Since it does not go or stay low, we measured the Fault and Enable pins:

CH1: Gate
CH2: IN (IN+ - IN-)
CH3: Fault (Pin 13)
CH4: EN (Pin 14)

The Fault Pin drops a bit during the turn on, but the Gate rises. After ~6µs the gate turns off but IN, EN and Fault are completely stable at this point.

We also found out, that the driver is working with some duty cylces and will continue to not work for ~550µs once it stopped working before trying to turn on the gate again.
CH1: Gate
CH2: IN

I marked in green the areas of the duty cycle where the driver was working, and in red the ones where it didn't turn on the gate. Especially interesting are the short pulses after 550µs staying low where it tires to turn on the gate but shuts it down again before the IN signal falls low.

I'm quite out of Ideas what to measure on the driver PCB. We will now try to reduce the coupling capacitance of the AC-High voltage to the Low-Voltage side by adding CMCs in the supply and separating the high and low side driver, since we only get this behavior on the low side. I would highly appreciate it if you could give us a hint on how we could get rid of this problem.

Kind regards

Bernhard Baier

  • 0
    TI__Mastermind 20326 points

    Hi Bernhard,

    RDY and FLT are supposed to be outputs, so the voltages you observe show noise injection, not a power supply droop or a fault detection.

    There is a lot of noise coupling into the input side during the common mode spike. Since the issue only appears at >750V, I suggest increasing the values of the IN+ and IN- capacitors. There might be enough charge injected into the inputs to change the input state. 

    The C23_GDB= 18pF DESAT capacitor looks too small. Does this issue persist when you short DESAT and COM?

    Also, these types of issues can usually start to arise when there is high switch node ringing. Do you have any measurements of the half-bridge's switch node? Hopefully the HV Bus decoupling does not allow significant ringing.

    Best regards,

    Sean

  • 0 in reply to Sean Cashin
    Prodigy 10 points

    Hi Sean,

    we reduced the coupling capacitance from the isolated DCDC by placing a CMC on the low voltage side. This reduced the noise on the low voltage signals. We still get the same issue though.

    I shorted DESAT and changed C23 to 10nF both tests were unsuccessful.

    I measured the switching behavior on low side at 800V with no load and can mainly see interferences on the low voltage side:

    CH1: Gate
    CH2: Drain - Source
    CH3: IN-
    CH4: IN+

    I then changed the time range (on the top) and zoomed in on a "working" turn on:

    As you can see, the driver switches on the FET every ~750µs and stays low in-between. 6µs after the turn on the gate voltage is falling again but the drain voltage does not change since the top FET does not turn on and there is no load. 2µs later the gate is turned on again and returns to low after ~1µs. There is no fault or RDY going low. Since the drain voltage does not change when switching off the gate there is no EMI and all signals are perfectly stable except for the gate. On the second turn on there is no EMI on the signals but still the driver switches off again.

    We will try to further decrease the capacitive coupling to the low voltage side and increase some filter capacitors, since we think this might be the cause. We can't understand why the driver switches off without asserting a fault therefore we will focus on the low voltage input signals.

    I hope you can give us another hint.

    Kind regards

    Bernhard

  • 0 in reply to Bernhard Baier
    TI__Mastermind 20326 points

    Hi Bernhard,

    Based on all these details, I agree that we should look at the inputs. I have had a similar waveform when I have tried to use a differential input that was not truly symmetrical. Could it be related to deadtime in your interlocking circuit? Does the behavior change if deadtime is adjusted?

    You can strengthen the input drive (lower input impedance) by shorting R19 and R20, which are now 47 ohms. You can also use 1nF capacitors here.

    The only other thing would be Vcc UVLO, but that should report a low RDY pin signal. What is the target final voltage? How close are we at 750V?

    Best regards,

    Sean

  • 0 in reply to Sean Cashin
    Prodigy 10 points

    Hi Sean,

    I'm not quite sure if I understand you correctly. The Inputs IN+ and IN- are not 100% differential since we have a dead-time in our signal where both inputs are pulled low. The differential input voltage IN = IN+ - IN- will be -5V then 0V for 300ns then 5V when we are turning on. I already tried to tie IN- to GND to use the driver single ended with no success.

    I tried 0R and 1nF at the IN pins with no success. I also increased the PullUps on RDY and Fault to 120Ohms (just for one test) with no improvement.

    I don't think that the UVLO is asserted since RDY stays high and the analog PWM is continuing to work. The target voltage would be 950V so we are way off.

    I measured the OUTH and OUTL pins to see if there is some ringing:
    CH1: Gate at FET
    CH2: Drain Source Voltage
    CH3: OUTH
    CH4: OUTL

    There is a small ringing on OUTH as the FET is switching, which cannot be seen at the Gate itself. But I don't think this should disturb the Gate Driver.

    I removed the DESAT barrier diodes to reduce the capacitive coupling and shorted DESAT with no effect. So I don't really know how to reduce the capacitance any further...

    Since I'm really out of ideas what to measure, I will have to take a look into different ICs. I tried the UCC21710 with the OC input, which had the same error. I will now test a different manufacturer to identify if this behavior is only specific to the UCC217xx ICs.

    Kind regards

    Bernhard

  • 0 in reply to Bernhard Baier
    TI__Mastermind 20326 points

    Hi Bernhard,

    You even changed the device to UCC21710 and had the same error? My next guess would have been that there was damage to the gate driver unit. 

    I am sorry we could not figure this out. I will continue to seek advice internally to try to figure out what could be causing this issue. 

    The fact that the gate driver output works normally at a lower voltage makes me think it is a noise injection issue, but it seems you have tried improving the noise filtering without success.

    One last test I will suggest is to use a 0V negative supply. I have found that having a negative turn-off voltage reduces noise immunity for this device in some cases, specifically nFLT nuisance triggering.

    Best regards,

    Sean