Tool/software:
When a voltage fault is detected by a monitoring channel of TPS38900-Q1 how is the fault reported and how is the fault cleared?
Hello,
In the following example the input voltage applied to MON3 is seen to exceed the programmed OV thresholds of the device. As illustrated in the figure, at the moment the input voltage exceeds the OV thresholds NIRQ and NRST assert (mapping is assumed). At the time the OV threshold is sensed the fault reporting register is updated to signal a fault. In the case of this example registers INT_OVHF (0x16) and INT_OVLF (0x18) of BANK 0 are updated, as illustrated in figure x. Note registers INT_UVHF, INT_OVHF, INT_OVHF, and INT_OVHF are structured such that the LSB reflects the status of MON1 and subsequent bits report status of subsequent monitors.
Registers INT_OVHF and INT_OVLF are updated to a value of 0x04h when the OV fault is detected. This signals that an OV fault has been detected on MON3 on both the HF and LF sense paths. Note that regardless of the status of the register NRST will de-assert when the voltage enters the valid widow once again. In the case of NIRQ the output will only de-assert when the error reporting register is cleared. The register signaling the fault can be cleared by performing a write one to clear (W1C) operation, on the fault reporting registers. It is good practice to I2C read all the voltage reporting interrupt registers to determine the fault experienced. Once determined, perform a write command to the register in question to clear the register. The sequence below is what a I2C transaction would look like for this example to clear the fault on MON3.
Regards,
Oscar Ambriz
