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BQ25703A: Application issues

Part Number: BQ25703A

Tool/software:

Hi

When using BQ25703A to charge the battery in buck mode, with 20V input and 8V output, there is no abnormality in the waveform of the G pole of the two MOS transistors; If it is boost mode, 5V input, 8V output, and the G poles of two MOS transistors overlap, how to solve this situation because there is a platform voltage on the upper transistor;

  • Hello Zhong,

    The Application Engineer that supports this device is out of office today, and tomorrow is a TI holiday. He will return next week to halp answer your question.

    Thank you for your patience.

     

    Best Regards,

    Christian

  • Hi, Susan,

    If you plot out VGS for both top and bottom FETs, you won't see any overlap. I don't see any deadtime concern here. 

    The VG of the top FET is misleading, its level can't reduce quickly to ground level due to VSW node voltage. 

    Regards,

    Tiger

  • Hi Tiger

    Thank you very much for your answer. I still have some questions to ask

    1)I retested the VGS voltage of the upper and lower MOSFETs and found that the dead time for the upper and lower MOSFETs to turn off and on is asymmetric, as shown in Figures 1 and 2. What is the reason for this asymmetry?

    2)2) If the dead time is increased by configuring registers, what impact will it have? I understand that it will increase power consumption because of the parasitic diode in the bottom FETs

  • Hi, Susan,

    Your measurement is probably incorrect. Did you get the same efficiency as TI EVM?

    Regards,

    Tiger