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TPS65220: RV/nINT mask problem

Christian Ziep
Prodigy 10 points
Part Number: TPS65220
Other Parts Discussed in Thread: TPS65219

Tool/software:

Hello,

we've got a problem with the IC. In some cases the nINT pin toggles to low due to an RV event (most likely due to an external EMI event, not at start up). The voltage of all rails is still fine even if this happens and there seems no problem with the connected circuit which is powert by the PMIC; only the RV register of the one or other LOD indicates a problem. Therefore we tried to 'mask' this issue because our connected error LED is fired using the corresponding pin. However the nINT pin will still driven low. Also a cold reset using pin 28 works fine but the nINT is still low after that.

Is there a reason for 'mask' this isn't work as expected?

Is there bany other way to clear the corresponding register other to set is using I²C interface? If no, which command we have to send via I²C to clear the nINT register and toggle the pin back to high state?

What else we can do to prevent such issue?

tnx, Christian

  • 0
    TI__Expert 6225 points

    Hi Christian,

    Thank you for reaching on e2e.

    Try setting the bit4 [MASK_INT_FOR_RV] in register MASK_CONFIG(0x25) to make nINT not sensitive to RV events.

    Sathish

  • 0 in reply to Sathish Vallamkonda
    Prodigy 10 points

    Hello Sathish,

    this is already done using the TPS65219_GUI ver. 1.0.2, but it does not work... (I tried this with several boards where the PMIC is build in, not only a singe one!)

    Regards

    Christrian

  • 0 in reply to Christian Ziep
    TI__Expert 6225 points

    Hi Christian,

    It is surprising that it shows LDO1 RV but the output is okay. Did you try writing '1' to the LDO1 RV bit in the INT_RV register to clear it?

    If not, we need to understand the reason for RV to show up.

    Sathish

  • 0 in reply to Sathish Vallamkonda
    Prodigy 10 points

    The INT_RV seems tp be a status-register. The issue is reported there but i'm not able to override the very bit using the evaluation software tool. No matter if i use 'Immediate Write' or 'Deferred Write'. After dumping the 'new' bit sequenz data to the PMIC  and re-read it the display does not change nor the pin voltage at nINT.

  • 0 in reply to Christian Ziep
    TI__Expert 6225 points

    Hi Christian,

    RV bit is set during rail turn on but MASK bits are loaded from NVM, for them to be effective we have to burn the value into NVM.

    First let's try if this works. After power up, disable LDO1 and set the MASK_INT_FOR_RV bit and then turn on LDO1 and see if INT stays high.

    I see the MASK_EFFECT bits in register 0x25 are set to 01, for the bit to not show the fault, need to set this to 00 before turning on LDO1.

    If this works, we can burn these bits into NVM.

    Sathish

  • 0 in reply to Sathish Vallamkonda
    Prodigy 10 points

    Hi Sathish,

    I have tried to do what you suggest, but it is not changing the state of the nINT pin when an RV event happens.

    1. first I disabled all LDO's

    2. changed the sequences to: MASK_CONFIG 0x25 --> (0x90) 10010000

    3. then I re-enabled the LDO's

    4. dump to NVM was done (bit sequens holds after read back)

    5. then I shut down & restarted the IC

    To simulate an RV event and to test if the masking works I injected a 3.3V LDO output with a function generator (also 3.3V) and performed a hard reset with pin#28...
    (whereby the rail could not be discharged from the point of view of the LDO).  

    The result is that nINT is still set to low, but the LDO supplies 3.3V.

    configuration of LDO1:

    (we power the PMIC using 3.3V input voltage)

  • 0 in reply to Christian Ziep
    TI__Expert 6225 points

    Hi Christian,

    if the PMIC is shutdown and re-started then it will not hold the new sequence written in step2.

    You have to simulate RV event after step3. Can you try that and see if nINT stays high?

    If this works, i can show you how to burn the new settings into NVM so that it works even after shut down and re-start.

    Sathish

  • 0 in reply to Sathish Vallamkonda
    Prodigy 10 points

    Hello Sathish,

    up to now i was not able to mask these RV events permanently following your descriptions. However i noticed that register 0x32 has to be cleared also (0x80 --> 0x00) to toggle nINT back to high state.
     
    In the browser software 'TPS65219_GUI/ver/1.0.2' we've to press the btn 'write' twice otherwise it doesn't work.

    Regards

    Christian

  • 0 in reply to Christian Ziep
    TI__Expert 6225 points

    Hi Christian,

    0x32 is for Timeout issue, may be rails are taking longer to come up?

    If you want to burn any of the new settings into NVM (for them to retain even after power cycle), please follow the NVM burn process steps in the NVM programming guide. Follow the 5 steps in the below document (page 9 or 23).

     https://www.ti.com/lit/pdf/slvucm5

    Sathish