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TPS6594-Q1: TPS6594-Q1

Part Number: TPS6594-Q1

Tool/software:

I need to propose system design in my project and I have one question on Watchdog failure Reaction in TPS6594

My understanding is in whether watchdog is configured in Triggered mode or Q&A mode, in case of failure (Timeout/no refresh received from SOC/Microcontroller) PMIC will react by nRSTOUT and nRSTOUT_SoC. 

Is my understanding correct ? 

Or 

PMIC will react only by error pin trigger (EN_DRV and nINT)

  • Hi Manish,

    Reaction can be defined by PFSM and internal HW control. Usually nRSTOUT and nRSTOUT_SoC (PFSM controlled) are pulled low as well as nINT and EN_DRV (HW controlled). 

    Do you have OPN to share or is this for new opportunity?

    Br, Jari

  • Hello Manish,

    All of our catalog releases (that you can buy from ti.com) have the behavior as Jari describe where only nRSTOUT & nRSTOUT_SoC are toggled, as soon as the error is flagged the nINT & EN_DRV are pulled low.

    Adding to what Jari describes for the hardware (nINT & EN_DRV), any time an interrupt is detected the nINT is pulled low and at that time it is the expectation that the MCU reads back these registers, does fault handling, and clears the interrupt.

    The EN_DRV works slightly differently, it can only be written to high or low by I2C/SPI when the device is a known good state, hence why it is called HardWare controlled. So when an error occurs the device pulls the EN_DRV pin low.

    Here are the requirements for the EN_DRV pin to be toggled arbitrarily HIGH or LOW:

    • Enable Drive (EN_DRV)
      • The following needs to occur for the EN_DRV to enabled
        • WD disabled or (ENABLED & OUTSIDE of LONGWINDOW)
        • All interrupts needs to be cleared
        • ESM either in ACTIVE or disabled, same as the WD

    If you want more custom fault handling for the WD error that can be done, but the PMIC programming will have to be custom.

    BR,

    Nicholas McNamara