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LM5148: Detailed description of prebiased startup process - bootstrap charging and transtion from DCM to CCM

Aidan Walton
Prodigy 80 points
Part Number: LM5148
Other Parts Discussed in Thread: LM5145, , LM5149

Tool/software:

Hi,

I have been digging around for some details about exactly how TIs family of synchronous buck controllers actually deal with the problem of start up when the output voltage is pre-biased and has a voltage either none zero but below set-point or even where the output is above the desired set-point and is gradually collapsing to below the switcher set-point. 

I have found some brief comments regarding the LM5145 behavior.. https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/952519/lm5146-q1-how-does-pre-biased-startup-work

This discusses the idea the the controller monitors the FB voltage and when it is above the ref (either SS or Vref) it recognizes this 'special' condition and switches the on the low side FET until the zero cross detector is triggered. If this is true, at  what threshold is the zero cross detection set -5mV, 0mv or 200mV. Normally during SS DEM is forced on and therefore this threshold would be 0mV or very close to 0mV.

The TI expert also describes this as a 'kind of' reverse boost converter action, and this is indeed clear, he then alludes to the problems that could arise from doing this. that being, when the low side FET switches off, it will potentially force current from output to input through the body diode of the high side FET, and maybe even damage the input vin / bias. I assume this is particularly concerning if the input stage is protected with an in line diode, as recommended in the datasheets. I have not attempted any formal analysis of this condition. But I assume as a TI engineer is discussing it. It must be a valid and concerning operation state.

Therefore, is this description accurate? Is this actually how the controller ensures that the bootstrap capacitor is charged? How many times does this switching occur, does it constantly do this until the ref voltage (SS or vref) has risen above the FB voltage?

Or is this entire description describing something that this controller does do, or is the author describing something that has been avoided in the LM5148 by using some alternative approach. It is not clear and to be honest, I still do not have a detailed step-by step understanding of exactly what the controller does to manage these conditions and what I should be concerned about in terms of damage to the IC under all possible scenarios?

Thanks, looking forward to a response.

  • 0
    TI__Mastermind 40060 points

    Hello Aiden,

    If your concern is regarding ZCD comparator and pre bias start up, the LM5148 handles this the same way as other TI Synch buck controllers in the LM514x family. 

    During start up, the device prevents current flow in a positive direction through the LS MOFET- (D to S)  and therefore avoids sinking current from the output to the input preserving Pre-bias conditions.  The LS MOSFET will not sink current until SS progresses and the FB voltage rises above the pre-bias voltage. The boot strap capacitor is still able to recharge during the very short off times that are still preserved under these conditions.

    I hope this addresses your concern.  feel free to follow up with more detailed questions if needed.

    Thanks.

  • 0 in reply to David Baba
    Prodigy 80 points

    Thanks for the response. I am however still lacking some more specific details. 

    I am still confused about how exactly this works. From my understanding the normal mode of operation in DEM is that after the high side FET has completed its conduction cycle. The low side FET will be switched on after the dead-time and will stay on until the D-S voltage of the LS FET has exceeded the ZCD threshold. In this situation where the current in the primary inductor is flowing towards the output, this is understandable as the D-S voltage of the low side FET will initially be negative based on the forward bias drop across the body diode. As the low side FET switches on the D-S voltage will be dictated by the current in the inductor as it ramps down towards zero and the Rds on of the FET, but as the inductor current approaches zero it will come closer and closer to 0V but will always be negative.

    However when the bootstrap capacitor has not been charged as is the case with pre-biased output, the high side FET can not be switched on. There must be an initial switch on of the LS FET pulling the SW node to GND, in order that the bootstrap charges from Vcc. 

    Do I assume therefore that the LS FET switches on for the absolute minimum off time (~90nS) before it is then instantaneously switched off because the ZCD threshold is triggered due to the current flow in the primary inductor actually being the reverse of normal and therefore D-S voltage of the LS FET will always be slightly positive.

    Do we assume that the current that can build up in the reverse direction is very small because the on-time of the LS FET is so small, it simply does not have much time to ramp up. Furthermore, do I assume that because this current level is relatively low, the subsequent rise of the SW node voltage and dump of energy through the HS FET's body diode is insignificant? If I understand correctly however, the low side min-off time is longer than the HS min-on-time 90ns versus 50ns. At the very instant that the FB voltage rises above the SS ramp the HS FET will also be switching close to its min on time, and therefore for a short period net energy would flow from output to input.

    Is this really of no concern?

    Furthermore could you explain the benefit of ramping the ZCD threshold from 0 towards 200mV after regulation is achieved. The datasheet of various members of the LM514X family mention that the transition from DCM to CCM takes place over 1000 cycles. As the ZCD threshold moves from 0 - ~200mV. I am assuming this allows any low load reverse current flow in the primary inductor to build up gradually. But why? What would be the impact of a harsh transition from DCM to CCM and once again does this have any effect of the integrity of the integrated circuit?

    Thanks again

  • 0 in reply to Aidan Walton
    TI__Mastermind 40060 points

    Hello Aiden,

    DEM mode prevents current flowing from D-S, current is allowed to flow from S-D when its loaded.  DEM is always implemented at start up.  In the event of Boot UVLO, the LS MOSFET will turn on for a short period of time to implement boot refresh.  Not going to get into the details of how we implement this, but just to say we do it in the effort to protect the load and ensure we do not fail to start.

    Even in the event of a minute amount of negative current flow, the diode at VIN that you mentioned is not in the power path, so the Body Diode of the HS FET will conduct during this time to allow the current to flow to VIN.  This may result is a small step at VIN during this period of time.

    The benefits of ZCD walking out are to minimize perturbation at VOUT as it transitions out of DCM to CCM as the case may be, minimizing voltage perturbation during this step.

    Hope this helps.

    David.

  • 0 in reply to David Baba
    Prodigy 80 points

    Thanks David,

    Okay so this is similar to what I expected, it seems that unless you have a stupidly small amount of input bulk capacitance this pumping effect is of little concern.

    I would ask that if possible you share some more details about the boot refresh. The reason is I am developing a spice model for the IC. As I have already with many TI chips where a model is not available. It is when developing the model that subtle and specific implementation details become important.

    It is my role as a hardware developer within my company to ensure that any device that we have in our inventory of 'selected' components, can be used in simulation. We are very strict about this as it helps us to significantly reduce the number of design iterations. 

    However clearly this relies on good models. If you can help me to develop these more accurately it is a major help for us and avoids me having to guess what the device is doing internally.

    Any assistance much appreciated.

  • 0 in reply to Aidan Walton
    TI__Mastermind 40060 points

    Hello Aiden,

    Unfortunately, some of the level of detail you are asking will need an NDA for us to disclose when the higher level of detail.  We have a PSPICE model online, suggest using this.

    Thanks.

    David.

  • 0 in reply to David Baba
    Prodigy 80 points

    Thanks, I don't see the spice model on the product page. 

    Although I appreciate your reasons in some ways. I would say that I will just have to guess at what the chip does, or reverse engineer what I can. It would have been a lot easier if you decided to help.

    Maybe we could have an NDA? Do you have a formal mechanism in place?

    Thanks all the same.

  • 0 in reply to Aidan Walton
    TI__Mastermind 40060 points

    Hello Aidan,

    Check out the LM5149 it's the same device without AEF.  For NDA, please follow up with your local TI sales Rep.

    Thanks.

    David.

  • 0 in reply to David Baba
    Prodigy 80 points

    Thanks David,

    Yeah, but it is encrypted and we don't use PSpice. Thanks anyway.... long live free beer!

  • 0 in reply to Aidan Walton
    TI__Mastermind 40060 points

    Aidan,

    Very sorry, for Encryption, you will need an NDA.

    David.