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TPS92692-Q1: The Switch current limit of TPS92692

zhang lin
Intellectual 340 points
Part Number: TPS92692-Q1
Other Parts Discussed in Thread: TPS92692

Tool/software:

I found while checking the manual that the TPS92692 has the following descriptions:

① Cycle-by-cycle current limit is accomplished by a redundant internal comparator. The current limit threshold is set based on the status of the internal PWM signal. The current limit threshold is set to 250 mV (typ) when the PWM signal is high and to 700 mV (typ) when the PWM signal is low.

② Cycle-by-cycle current limit is activated when the IS pin voltage exceeds 250 mV. The GATE and PDRV outputs are disabled, the SS and COMP pin capacitors are discharged, and the FLT pin is forced to ground.

I feel that these two conditions are a little conflicting.

By adjusting the IS resistor under MOS, it only "current limits" at low voltage; if the VIS voltage exceeds a "threshold limit", a restart will occur.What is this threshold?

I want to know under what circumstances the output current limit will be triggered and under what circumstances the chip restart will be triggered?

  • +1
    TI__Expert 6220 points

    Hi Zhang,

    Great questions.

    zhang lin said:
    ① Cycle-by-cycle current limit is accomplished by a redundant internal comparator. The current limit threshold is set based on the status of the internal PWM signal. The current limit threshold is set to 250 mV (typ) when the PWM signal is high and to 700 mV (typ) when the PWM signal is low.

    As it states, these thresholds are only relevant when using internal PWM dimming, otherwise the threshold is set to 250mV when internal PWM dimming is not in use

    zhang lin said:
    By adjusting the IS resistor under MOS, it only "current limits" at low voltage; if the VIS voltage exceeds a "threshold limit", a restart will occur.What is this threshold?

    This threshold is 250mV as long as you aren't using internal PWM dimming.

    zhang lin said:
    I want to know under what circumstances the output current limit will be triggered and under what circumstances the chip restart will be triggered?

    So, depending on the fault, the device will either simply force the nFLT pin to GND or it will actually shut off the IC.

    If the fault simply forces the nFLT pin to GND, you have flexibility with the design and you can utilize the nFLT pin however you wish:

    "The device indicates a fault by forcing the open-drain fault indicator FLT pin to GND and initiating a 36-ms timer.
    The devices do not internally initiate any protection action and continue to operate until externally disabled by
    pulling SS pin to GND. This provides maximum design flexibility to enable user defined fault protection by using
    either the fault indicator output, FLT, or the analog IMON output based on the LED driver topology and end
    application.
    The undervoltage fault detection circuit is internally disable based on the SS pin voltage and internal PWM
    status. The fault blanking circuit is designed to prevent false undervoltage detection during the startup sequence
    and PWM dimming operation."

    The chips actions based on certain faults are listed in this table below:


    This table explicitly states when a fault only forces the nFLT pin to GND or if the fault shuts off the circuit entirely.

    Please let me know how I can further assist you.

    Best,
    Daniel