TPS6594-Q1: Pullup power rails for TPS65941319-Q1

Michael Ye

Part Number: TPS6594-Q1

Tool/software:

Hi,

The TPS65941319-Q1 PMIC User Guide for AM65 Sitara Processors has a table stating PMIC_nRSTOUT should be pulled up to VDA_MCU_1V8:

However, Figure 3-1 of the document shows the I/O supply pin, VIO_IN, being powered from a 3.3V rail:

This seems to contradict the datasheet for the TPS6594-Q1, which indicates nRSTOUT is within the VIO domain.

Since VIO_IN is powered by a 3.3V rail and nRSTOUT is within the VIO domain, shouldn't it be pulled up to VDD_MCUIO_3V3 instead of VDA_MCU_1V8?

Please advise. Thank you.

1 month ago

+1 Nicholas McNamara 1 month ago

TI__Mastermind 19277 points

Hello Michael,

You do make a very good point, this is an oversight, the datasheet doesn't explicitly make it clear that the logic can be under the VIO input of the 3V3, only in the case of exceeding this value would I understand the concern. This is permissible, from a logical grouping of power rails and timing perspective please connect the PMIC_nRSTOUT pin to the VDA_MCU_1V8.

I hope this answers your question,

Nicholas McNamara

0 Michael Ye 1 month ago in reply to Nicholas McNamara

Prodigy 215 points

This does answer my question, thank you!

0 Michael Ye 1 month ago in reply to Nicholas McNamara

Prodigy 215 points

By the way, what would be the downsides of connecting PMIC_nRSTOUT to VDD_MCUIO_3V3?

0 Nicholas McNamara 1 month ago in reply to Michael Ye

TI__Mastermind 19277 points

Hello Michael,

I made the comment of timing, but there could be other such as split domains, the recommendation is there to ensure that all features are available.

BR,

Nicholas McNamara

Power management

Power management forum

TPS6594-Q1: Pullup power rails for TPS65941319-Q1