LM74912-Q1: condition to latched off

Part Number: LM74912-Q1
Other Parts Discussed in Thread: LM74912

Tool/software:

Hi all,

8.3.5 Low IQ SLEEP Mode (SLEEP, SLEEP_OV)

in the manual.

’’As an additional layer of protection, device also features thermal shutdown with latch off feature in SLEEP mode in case of any overheating of the device in SLEEP mode. ’’

So my understanding is this device latches off
・when overcurrent protection is in place
・Thermal shutdown when in sleep mode

Is my understanding correct? Are there any other conditions to latch off?

Best Regards,

Ryusuke

  • Hi Ryusuke,

    Your understandings are correct.

    When not in sleep mode, the device will latch-off with short circuit protection as well.

    Regards,

    Shiven Dhir

  • Hi Shiven,

    If the voltage of the source side of the FET in the latter section rises and then falls, does it latch off?

    The phenomenon occurs and we are looking for a solution.Is there any solution?

    Best Regards,

    Ryusuke

  • Hi Ryusuke,

    In this case, it won't latch-off. Although you can refer OV ladder to VOUT for clamp operation.

    Regards,

    Shiven Dhir

  • Hi Shiven,

    My customer uses this device the following configuration.

    The waveform is shown below.

    A(VDD12):Vin

    OUT(VDD2):Vout

    The electrical potential of the CS+ signal is rising.
    Only at this moment, it appears as if the current of several hundred uA is output from the CS+ terminal, causing the potential to rise.
    (Originally, the CS+ terminal draws a current of 11 uA.)

    1) Is the potential of the CS+ rising immediately after the Q1 gate is switched from ON to OFF, causing the current to flow back from the CS+ to the C side?

    2) Is there any countermeasure for the above?

    Best Regards,

    Ryusuke

  • Hi Ryusuke,

    The shared waveform is very hard to read, and the power rail seems to be very noisy.

    Is the concern related to CS+ being higher than C?

    Regards,

    Shiven Dhir

  • Hi Shiven,

    I'm sorry it's hard to read. I'll resend it again below.

    1) I will check to the customer that the power rail is out of order.

    2) ''Is the concern related to CS+ being higher than C?''

      →Yes. We understand that CS+ will have a lower potential than C.

    Best Regards,

    Ryusuke

  • Hi Shiven,

    Since there is noise in the VIN, we proposed to evaluate it without noise.

    On the other hand, in the data sheet, page 23, it says that it withstood AC noise in the LV124 test.

    Is this IC vulnerable to noise superimposed on the VIN?

    How can we improve the noise test resistance?

    Below is the configuration of my customer.

    Best Regards,

    Ryusuke

  • Hi Ryusuke,

    Yes, LM74912 is capable to withstand AC superimposed signal on VIN.

    Controller is supposed to react to any kind of reverse current flow and block it.

    You can add an RC this way to delay the response time.

    Regards,

    Shiven Dhir

  • Hi Shiven,

    In our customer's waveform, there is certainly ripple in VIN. However, it is smaller than 2V, and I expect IC to operate without any problem.

    If AC noise comes into VIN,

    why does the C++ potential rise? I would like to know how the VIN noise appears at the C++ terminal.

    From the waveform, I observed the VIN jumping up just before the overcurrent event occurs. However, the C++ pin voltage does not rise at this time.

    I would like to know why this difference occurs.

    The our customer is using RC with the following value.

    It would be great if you could comment on it.

    Best Regards,

    Ryusuke