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UCC21750-Q1: I would like to inquire about the circuit design of the UCC21750 schematic and layout design guideline

Junehee Park
Intellectual 320 points
Part Number: UCC21750-Q1


Tool/software:

Hi~

The guideline states to apply a Bead to the FET Gate as follows ( file name : UCC217xx Schematic and Layout Design Guidelines_RevA.xlsx)

If a bead is added, its purpose should not be to control noise from the gate driver to the FET, but rather to minimize the impact of noise generated by the FET on the gate driver.

The location of the CL (capacitor) should also be moved to the front side of the bead, and the clamp diode should likewise be positioned before the bead.

Please confirm if this is correct.

  • 0
    TI__Expert 6730 points

    Hi Junehee, 

    Yes, your understanding is correct. Gate ringing can be detrimental to the gate driver since noise coupled onto OUTH and OUTL can exceed device absmax and damage the gate driver. 

    Vivian

  • 0 in reply to Vivian Qi
    Intellectual 320 points

    Are you saying that the circuit in the guide document is wrong and the circuit I suggested is correct?

  • 0 in reply to Junehee Park
    TI__Expert 6730 points

    Hi Junehee, 

    Apologize - I misread part of your question. The clamps are placed close to the gate in the schematic guideline so that the power switch can also be protected when gate ringing happens. Usually power switches have a maximum Vgs/Vge rated voltage, and large gate ringing can exceed that voltage limit. 

    As of CL, I've seen customers doing it either way - placing them closer to the gate driver ("before" the bead) vs. placing them closer to the power switch ("after" the bead). The main purpose is to dampen the noise in the gate loop, so either way should work. 

    Thanks, 

    Vivian