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TPS92624-Q1:Inquiry About Availability of Detailed Logic Block Diagram for TPS92624-Q1

Part Number: TPS92624-Q1


Tool/software:

ear TI Support Team,

Hello,
We are currently developing an automotive LED driver circuit and have adopted the TPS92624-Q1 as a key component in our design.
We truly appreciate the technical documentation provided in the datasheet, which has been very helpful.

However, the functional block diagram (Figure 7-2) and the I/O structure (Figure 7-11) are presented at a high level of abstraction, making it difficult to clearly understand the internal operation of the Logic block — particularly in the context of design reviews and FAULT Bus implementation.

To ensure system reliability and safety, we would like to inquire whether it is possible to obtain more detailed documentation or an internal block diagram that covers the Logic block, including the following aspects:

Pushpin Specifically, we are looking for information on:

Internal decoding of PWM input signals and per-channel dimming control

Diagnostic operation flow (e.g., LED open/short detection, overcurrent conditions)

Behavior of the FAULT pin (input sensing vs. output sinking logic)

Effect of the DIAGEN pin on diagnostic operation and output shutdown behavior

This information would serve as an essential reference for designing a robust FAULT Bus configuration and implementing reliable per-channel current control logic in a multi-channel system.

If there are any application notes, internal block diagrams, or flowcharts related to the items above, we would greatly appreciate it if you could review the possibility of sharing them.

Thank you very much for your support.

  • Hello Lim,

    Thank you for your question but unfortunately we are not able to provide detailed internal design information.

    However, I would like to point you towards section 7 in the datasheet. This includes timing diagrams and short/open fault scenarios that should support your application needs.

    For example, this table in 7.3.9 shows the fault behavior specifications you mentioned.

    Additionally, we are able to sample the device EVM to verify specific fault handling questions.

    Best,
    Isaiah