Tool/software:
I have a schematic and layout completed using the transistor as mentioned above, and I request assistance in reviewing the schematic and layout.
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Tool/software:
I have a schematic and layout completed using the transistor as mentioned above, and I request assistance in reviewing the schematic and layout.
Hello Pragash,
Thanks for your interest in TI FETs. Apologies for the delay. I missed your earlier private message. I can only review the FET (Q1) circuit as that is my area of responsibility and expertise. The Q1 schematic looks OK except for R1, a 0Ω resistor pulling the SENSORS_EN signal to GND. This will force the FET on. Not sure if this is your intention. R27 the 100kΩ resistor pulls the gate up to the source (3.3V) and makes sure the FET is off if the SENSORS_EN signal is open. Pulling SENSORS_EN signal to GND should turn the FET on if R1 is not populated.
Best Regards,
John Wallace
TI FET Applications
Hi Pragash,
Since we are communicating via PM, I will close out this thread.
Thanks,
John
Hi Pragash,
Thanks for reminding me. I missed this one. What is the reference designator for the switch?
Thanks,
John
HI Pragash,
The implementation looks good. Please let me know how it works.
Thanks,
John
John Wallace, does that mean the switch will be able to operate stably to switch ON and OFF the high power LTE Modem as in my schematic? I just wanted to verify. Moreover, the input voltage to the switch varies from 3V to 4.2V as it's shorted to the battery voltage.
John Wallace1, I have asked some questions about your answers. Please help answer them. Thank you so much.
THANKS John Wallace1. i started understanding things better. i have follow on comments and questions. please help to clarify them as well. so the switch can still work reliably in open drain (ON) and high impedance (OFF) correct? only problem is logic will not work.
Hi Pragash,
Driving the P-channel FET gate with a logic signal will not always work in this scenario because the battery voltage at the source is variable. In reading the MCU datasheet, the output logic high signal does not pull all the way up to the VCC rail powering the MCU. An open drain seems like the best approach. Turn the FET on when the open drain pulls low and turn the FET off when the drain is high impedance. You may need to adjust the resistor value (smaller) that pulls the gate up to the source if there is enough leakage current to charge VGS to a high enough that the FET starts to turn on. I'm assuming the high impedance state will have very low leakage.
Thanks,
John