UCD3138A: question about UCD3138A

Hello Jimmy,

An offset of 4ns would correspond to 1 PCLK of the UCD3138A (PCLK is a 250MHz timer). So, 4ns or 8ns delay/shift from the intended event would be an expected offset due to the oscillator/processor timing (Ex. if you try to sync 2 DPWMs together, often they may be 4ns apart due to it taking 1 PCLK cycle to sync). 45 ns, however, is quite a large difference that should not be caused by the UCD3138A itself. For 45ns offset to occur, I think something should be wrong with your code and the timings you set. 

Do you have any programmable deadtime in the code? Any fault, CBC or blanking times? Any clamping between the front end sensing and the DPWM event? Any interrupts? These could all be potential sources of delay.

FYI, July 4th is a US holiday. Please expect a delay in further responses.

Regards,

Jonathan Wong

Hello Jonathan：

The current application is fixed dead zone and open-loop operation, fault，CBC，blanking time， There should be no clamping or interruption, and the customer also believes that it should be related to software settings or peripheral circuits. Does TI recommend a demo program for reference?
Additionally, there are actually two issues on the customer's end,
1. In the demo board test of ti, the cycle is stable, but it is about 45ns larger than the set value
2. Testing the same program on the customer's own board, the cycle begins to abruptly change, but the same cycle as the set value can be measured.

Hello Jimmy,

If the issue is related to software settings, then I would need to view the code to see if there are any issues. We do have existing UCD3138 firmware that I would recommend as a starting point as well as a way to compare if your settings are correct. They can also start with the UCD3138x training labs, which configure the UCD3138x in an open loop configuration in Lab 2. What topology is the customer using? 

By "fixed dead zone" do you mean fixed dead time? 

Regards,

Jonathan Wong

Hello Jonathan：

Yes,ucd3138 is worked on open loop mode, fixed deat time,frone_end,filters,are not work,and only dpwm0 is enabled.My customer‘s project is base on HSFB Frimware-1.1, but the code already changed too much .

Customer set the code run to idle state then turn on dpwm and stoped,here is code.

Hello Jimmy,

Thanks for confirming that their starting point was the HSFB EVM firmware. Can you please share the actual code instead of pictures? The pictures also do not really show much of the code. After all, the 3rd picture only shows commented out code and the code that is not commented out I cannot see what the KI_CLAMPs are equal to.

As a note, you can insert code in E2E by going to Insert --> Code and selecting C in the dropdown.

if(1)
{
    clear_filter0;
    clear_filter1;
    clear_filter2;
    LoopMuxRegs.DPWMMUX.bit.DPWM0_FILTER_SEL = 0;
    Filter0Regs.FILTERCTRL.bit.KI_STALL = 0;
    Filter1Regs.FILTERCTRL.bit.KI_STALL = 0;
    restart_counter = 0;
    FeCtrl0Regs.RAMPDACEND.bit.RAMP_DAC_VALUE = 93
    FeCtrl0Regs.EADCDAC.bit.DAC_VALUE = 9300;
    FeCtrl0Regs.DACSTEP.bit.DAC_STEP = 100;
    Fault_flag.bit.vout_ov = 0;
    

void init_dpwm0(void)

{
    Dpwm0Regs.DPWMPRD.all = PERIOD_H;
    Dpwm0Regs.DPWMEV1.all = EVENT1_H + DT;
    Dpwm0Regs.DPWMEV3.all = EVENT1_H;
    Dpwm0Regs.DPWMCYCADJB.all = DT1_H + D
    Dpwm0Regs.DPWMCTRL0.bit.PWM_B_INV = 1;
    
    Dpwm0Regs.DPWMCTRL0.bit.PWM_MODE = 2;
    Dpwm0Regs.DPWMCTRL0.bit.CLA_EN = 1;

Below are some more questions:

• What is the deadtime and DPWM period value? 
• What DPWM mode are you using? Why is DPWM EVENT2 and EVENT 4 not defined?
• Is only DPWM0 enabled or are other DPWMx signals enabled?
• Are there any syncing between blocks? (Ex. is DPWM1 synced to DPWM0)
• You said the operation is open loop. However, the first picture shows that the Front End is initialized for a ramp. Is this Front End ramp being used? What is the input to the filters?

Regards,

Jonathan Wong

Hello Jonathan：

The customer feedback on the questions you asked has the answers in the pictures provided above,
Among them:
PERIOD_H=16000,
EVENT1_H is 132*4
DT1_H is 90*4,
DT2_H is 40*4.
As for the value of KI_CLAMP, it does not work here

Please help check，Thanks！！！

Hello Jimmy,

I will continue to look into this issue and provide a response tomorrow.

Regards,

Jonathan Wong