Tool/software:
1. Is the FET mounted on the TPS7H4010-SEP a vertical structure or a horizontal structure?
2. You said that the radiation resistance has been strengthened, but what specific measures have been taken compared to conventional products?
For example, have you made the gate oxide film of the FET thicker, or made it more difficult for electrons in the gate oxide film to escape from the electrode?
3. When positive charge is trapped in the oxide film or Si-SiO2 interface states occur, the threshold voltage and current flow change. It seems that normal operation would return if the electrons and holes were combined by applying a gate voltage, but why does this not happen?
4. When I checked the internal circuit, I found that in addition to the FET, an EA and an op-amp are also mounted. Is it possible that these FETs are broken?
5. Are there any other possible causes?
6. Please let me know if there are any countermeasures.
