TUSB1142EVM: Why are CC1 and CC2 flipped on the schematic?

Hi,

Yes this is inverted twice. The CC controller used here is open drain, so it requires an external pull up to drive high. This mean that we will still be pulling up the signal when driving low resulting in contention. Due the nature of this pin we have to invert twice with mosfet to ensure function.

Hi Vishesh, 

Perhaps my confusion is from U8. I thought it was a N-channel MOSFET.

The part# suggests it is actually a Toshiba 2SK209-Y(TE85L,F) N-channel JFET. Is it actually a JFET? www.digikey.ca/.../4305048

I don't have a lot of experience with JFETs but it does not seem the JFET can be turned off as shown in the schematic because the GATE cannot be set negative relative to the SOURCE.

Please clarify:
1) Are U8 and U9 N-channel MOSFETs or a N-channel JFETs?

2) If it is a MOSFET, can you please provide the correct part#?

3) If it is a JFET, what is the principal of operation in the circuit?

Thanks

Hi,

Apologies I used MOSFET and JFET interchangeably in this application as the current drive and voltage drive is low.

The main difference between MOSFETs and JFETS is the gate. MOSFETS have an insulated gate and JFETS have a PN junction at the gate. This results in different performance, but in our case the function and performance will be the same as a digital inverter. (our function is too low power and noise tolerant for us to see any noticeable differences between MOSFET and JFET function).

Hi Vishesh,

I don't think an n-channel JFET can be used interchangeably with a n-channel MOSFET in this application. 

N-channel JFET is depletion mode, which means it will be ON when no voltage is applied to the gate. This is opposite to a N-channel MOSFET which is normally OFF with no voltage applied to the gate.

N-channel JFET will need a negative voltage at the gate relative to the source to turn off. In this application, the JFET does not turn off at all because the gate cannot be negative relative to the source.

If U8 and U9 are JFETs, neither will work as an inverter.

When I was measuring POLz line (measured at R17), it was toggling between 0V and ~0.6V with the two usb device orientations rather than the expected 0V and 5V.

1) In the Hi-Z state of POLz in one of the USB orientations, the 5V through 100k R17 is passing through the PN junction of the GATE-SOURCE JFET causing the 0.6V drop measured. JFET is ON in this state and 1142_FLIP measures near 0V.

2) With POLz pulled down to 0V in the other USB orientation, the JFET remains ON. The 1142_FLIP remains near 0V still.

So 1142_FLIP does not change with either USB orientation. I believe it was a mistake to use N-channel JFET instead of a N-channel MOSFET in this application.

Hi,

Apologies for the confusion, I will ask the designer of the EVM. I may have an incorrect understanding here. 

Hi Vishesh,

That answers my questions, thanks for your help.