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UCC28C43: Debugging High-Frequency EMI and Thermal Issues in BQ34Z100-G1 + UCC28C43 Push-Pull Isolated DC-DC Design

Part Number: UCC28C43
Other Parts Discussed in Thread: BQ34Z100-G1, UCC27714, , CSD19502Q5B

Tool/software:

Hello engineers,

I’m working on a 100W isolated push-pull DC-DC converter (24V in, 12V/8A out, 100kHz) using BQ34Z100-G1 for battery management, UCC28C43 as the controller, UCC27714 as the gate driver, and CSD19502Q5B NexFETs. We are facing:


Small orange diamond Persistent High-Frequency EMI Spikes:

  • Spikes at 180–250MHz aligned with leakage ringing and MOSFET switching edges.

  • Added a 100Ω + 1nF + FRD RCD snubber; partial improvement but increased switching losses and heating.

  • Spread-spectrum helped slightly, but spikes remain problematic for compliance.


Small orange diamond MOSFET Overheating Concerns:

  • At 80W continuous load, MOSFET case temp exceeds 85°C despite heatsinking and ~2m/s forced airflow, raising reliability concerns.

  • Adding shielding improves EMI but increases thermal resistance, leading to further heating.


Small orange diamond Gate Drive Speed vs. EMI/Efficiency Trade-Off:

  • Faster switching (high dV/dt) increases EMI significantly.

  • Slowing down with gate resistors reduces EMI but increases switching losses, raising temperatures.

  • Dead-time tuning is challenging to balance between avoiding cross-conduction and maintaining EMI performance.


Seeking advice on:

White check mark 1. Best practices for reducing leakage ringing without significantly increasing switching losses in a UCC28C43 + UCC27714 push-pull topology? (Feasibility of active clamp or dual snubbers?)

White check mark 2. TI-recommended procedures or practical tips for tuning RCD snubber parameters in push-pull designs without excessive power loss?

White check mark 3. Recommended dead-time adjustment ranges or methods with UCC27714 to prevent cross-conduction while controlling EMI?

White check mark 4. Proven layout and shielding practices for CSD19502Q5B NexFETs in high dV/dt applications to manage EMI while maintaining thermal efficiency?

White check mark 5. Any real project waveform comparisons or field-tested insights for system-level optimization of EMI and thermal management in similar designs?


Transformer leakage is ~1uH measured, PCB grounding and return paths are carefully optimized, and input filtering is solid.

Any reference designs, practical debug insights, or tested waveforms would be greatly appreciated to systematically optimize EMI and thermal performance in this push-pull isolated DC-DC setup.

Thank you in advance for your help!