Part Number: TPS552882-Q1
Other Parts Discussed in Thread: TPS552882
Tool/software:
I think I can sum up my confusion in two questions, then I'll go into more gory details below.
1) What is the guaranteed minimum gate drive voltage (V_DH - V_SW1) provided by the TPS552882? (I want to make sure the top buck FET (blue, below) is fully on)
2) Are there minimums on Vin and/or Vout to ensure the answer to the first question is valid?
I'll explain what I'm thinking if that helps clarify what I'm confused about.
The gate of the top buck FET is driven (with a loss of VDR1H_H) from BOOT1, which is charged from VCC (minimum guaranteed voltage 5.0V), through a diode loss whose forward voltage is not specified in the datasheet (yellow diode highlighted above). Assuming that drop is 0.3V, the drive strength would be 5V - 0.3V - 0.1V = 4.6V, which is nominally above V_GSmin of many FETs, but doesn't leave a whole lot of margin. This leads to my first question above.
Additionally, that first paragraph assumes that the VCC voltage is 5V. It looks to me like VCC is derived from an LDO which is in turn driven from the stronger of VIN and VOUT (described by Table 7-1), minus a drop out voltage (VCC_DO ). Short version -- VCC < max(VIN, VOUT). But the TPS552882 states that it can operate from inputs as low as 2.7V to provide outputs of 0.8V. What happens at start up if VOUT = 0 and VIN = 3.3V? (or any number of configurations where max(VIN, VOUT) < 5V). Where is sufficient voltage to turn on that top blue FET coming from? (second question above)
Thank you!
