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LMR36503-Q1: Please help me design an EMI filter by referring to the AN-2162 document.

?? ?
Prodigy 30 points

Part Number: LMR36503-Q1
Other Parts Discussed in Thread: LMZ23605

Tool/software:

I am using LMR36503RS3QRPERQ1 IC.

The frequency was set to 400 kHz by attaching 41.2K Ohm to the RT pin.

I confirmed that the frequency was operating at 60~70 kHz, not 400 kHz, because the load connected behind the buck IC was small.

When designing a CLC filter with reference to AN-2162 document, which fs value should I use, 400 kHz or 60 kHz?

And how do I find the Vin-ripple-p2 value?

Can you elaborate on the process of calculating the 'Cfb' value in Example 1 (LMZ23605)?

  • 0
    TI__Genius 15400 points

    Hi,

    For EMI critical applications, I would suggest going for the FPWM variant of devices. For those, you would not see the variation of frequency with load and the filter can be designed for the set frequency. In PFM, the frequency can vary widely during transients making filter design difficult.

    That being said, if you want to go for the PFM variant and load remains constant, you can use the observed frequency (60-70 kHz) for designing the filter. 

    The Vin-ripple-p2p value is the measured peak to peak amplitude of the ripple at VIN without the EMI filter.

    Once you calculate the required attenuation using eqn. (2) and the measured Vin-ripple-p2p, you can calculated the Cfb value using eqn. (5)

    Regards,

    Niranjan

  • 0 in reply to Niranjan Nair
    Prodigy 30 points

    When the Vin-ripple-p2p is approximately 63uV, the Att comes out to 35.98dB and the Cfb comes out to 2.49uf. Is this calculation correct?

    Does "Vin-ripple-p2p" mean V or dBV? If it's dBV, it should be the 'EST. NOISE LEVEL' listed in Table 5.1, but I don't get the same results.

  • 0 in reply to ?? ?
    TI__Genius 15400 points

    In that eqn. Vin-ripple-p2p should be entered in uV. One other thing : Input ripple should be measured across the input capacitor closest to device pin, ideally using a pigtail probe.

    63 uV seems quite low to begin with. This is without input filter right? Also, what is the input capacitance present?

  • 0 in reply to Niranjan Nair
    Prodigy 30 points

    63uv is not the value measured on my board.

    In Table 5.1, the Vin-ripple-p2p value is not indicated, so the calculated value to obtain 2.5 uF, which is indicated as the Cfb result value, was 63 uV.

    This is the measured EMI result when only the buck IC was assembled on my board. Do you have any advice?

    The output voltage is measured at 60~70 kHz and the EMI measurement value is measured in 3 MHz units.

    I am thinking of configuring a clc filter by setting the switching frequency to 60~70 kHz and 3 MHz.

  • 0 in reply to ?? ?
    TI__Genius 15400 points

    Hi,

    From the EMI results it seems the peaking occurs at around 100M. So a filter of cutoff around 60-70 kHz might not provide much use. Some steps you can try (in order) are

    1) Checking whether the layout follows datasheet recommendations (particularly, low SW node area, input caps and their placement)

    2) Using a snubber on the SW node. You can calculate the values from https://www.ti.com/document-viewer/lit/html/SSZTBC7

    3) Using a shielded inductor. Also, the short head of the inductor should be placed at the SW node for better performance

    4) Using a filter with cutoff around 1 decade earlier than the peaking, so around 10M bandwidth. However it should remain effective at 100M so you might want to use a ferrite bead instead of an inductor and small capacitors

    Regards,

    Niranjan

  • 0 in reply to Niranjan Nair
    Prodigy 30 points

    Thanks to you, I got some pointers for debugging.

    The EMI photo I captured was from a CE (Conducted Emission) test.

    Can layout check also affect ce test results?

    1) For the input capacitor, it was placed as close as possible to the back of the buck IC.

    1), 3) The shielded inductor and boot capacitor were also placed close to the sw node.

    2) Since there is no ringing at all in the buck output, it seems that there is no need to use a snubber.

    The document that reduces EMI in CE testing is 'AN-2162', so the focus was on the CLC filter described in this document.

    I'll try using the ferrite bead as you mentioned in number 4.

    Would it be okay to use it with a CLC filter at the board input? Or should I remove the CLC filter and just use the ferrite bead?

    I'm grateful for all the replies so far.

  • +1 in reply to ?? ?
    TI__Genius 15400 points

    Hi,

    The layout won't have much effect in CE apart from the input cap placement. Having an input filter would be the best option.

    Since the peaks are only just crossing the standard, you can have the cutoff frequency around one decade earlier than the peaks i.e. around 5-10 MHz. The filter should also be effective at the frequencies you want to filter out.

    So if going with a CLC filter you will need to make sure that the SRF of the inductor (and capacitors) are well above 100 MHz (or highest frequency you want to filter out). The better option would be to use a ferrite bead instead of the inductor as they typically have better characteristics at these higher frequencies.

    Regards,

    Niranjan