UCC5390: UCC5390SC being damaged.

Hi Ari,

This sounds like a common case of output-stage damage. Usually, it is related to high ringing on the switch node and the Vgs of the driven FET. Do you have any waveforms of the switch node (Vsw) or the gate-to-source voltage (Vgs)?

Here are my recommendations, in order of precedence.

1. You can usually dampen switch node ringing using the HV BUS rail decoupling. The switch node is shorted to the bus during high-side turn-on, and any switch node resonance also appears at the BUS. If you can critically dampen the BUS decoupling using electrolytic capacitors, then you can use full gate drive strength:

2. Otherwise, you can sacrifice drive strength and switching losses for a softer hit to the parasitic LC tank formed by the ldrain and Csw. Here is an example of the UCC5350 driving the NVHL080N120SC1 with Rg=1 Ohm. The Vgs is on CH1 and Vsw is on CH4.

One way to reduce ringing is to slow down the switching edge rate to below the resonant frequency. You can do this by increasing the gate resistor (here Rg=5)

3. Alternatively, you can add an external gate capacitor, which will add an AC load to the transient injection. As you can see, this increases the current load on the gate driver, and can even increase the Vsw ringing. (Rg=1, Cgs=1nF):

This is a SiC FET, which has low transconductance in its active region, during turn on and turn off. If you are using a Si FET, this kind of ringing will be much higher.

Best regards,

Sean

Hi Ari,

Could you draw a line on your above schematic where the VEE2-to-GND1 coupling is expected to occur? You say you have a neutral node that is referenced to VEE2 through a power supply?

One of the benefits of an isolated gate driver is that it decouples the output side from the logic level input. This allows higher ringing on the output before the logic-level input gets damaged.

If you have high coupling from VEE2 to GND1, then it seems possible that high dV/dt could be injected across VCC1-GND1. This device has edge-triggered ESD cells, and if the input supply is exposed to >5V/us, these will turn ON. Unless you limit this current, the resulting shoot through current could damage the ESD diode and cause a parallel path for input current.

Could you try putting a TVS clamp across this 5V power supply? That should help externally protect the internal ESD cells. TVS0500 is a possible option.

Best regards,

Sean

Hi Ari,

Thank you for the equivalent schematic. If I interpret this correctly, there is an AC short between GND1 and VEE2.

"Defect" means that something was wrong with the gate driver when it left the factory. I wouldn't use that word here, where external stress is more a likely root cause, given the correlation between layout location and damage.

 Yes, a transient at GND1 can lead to higher I(VCC2), as I mentioned last post. You have 100nF across the input supply, which should help significantly. Is it placed very close to pin1 and pin4? Optimizing this layout may be all that is needed. Otherwise, TI does sell additional external TVS devices that should activate before the internal ESD protection, which is my theory of the damage.

What was the dV/dt of your 12V input? You would need >5V/us on the power supply for >5V for the edge-rate triggered ESD diode to turn on. The only way I can get that kind of edge rate is with a hot-plug-in of a higher voltage. You could try taking a power supply and tapping a -12V connector to GND1. That would abruptly increase the supply voltage at a high edge rate. The supply voltage would still be <35V, but the fast edge rate could cause damage.

Best regards,

Sean

I think dV/dt on the input supply, leading to ESD damage, is a good guess. To prevent dV/dt on the supply, you can try moving the 100nF capacitor closer to the device. Adding a TVS device externally will also protect the internal supply ESD cells from damage.