TPS61299: Down Mode

Dice-K

Part Number: TPS61299

Tool/software:

Hi support team,

I have a question about this sentence in 7.3.8 Down Mode:
「In this way, the voltage drop across the PMOS is increasing as high as to regulate the output voltage.」

I assume that the increased voltage drop across the PMOS-FET will temporarily decrease VOUT.
So does that mean there's a need for boosting?

Regards,
Dice-K

27 days ago

0 Nini Zhong 27 days ago

TI__Genius 13075 points

Hi Dice-K,

please refer to this figure for Vout regulation. During down mode, Vout is still at the target value.

0 Dice-K 27 days ago in reply to Nini Zhong

Mastermind 7460 points

Hi Nini,
Thank you for your reply.

I would like to know the principle behind down mode.
Down mode only activates at plus 100mV.
Does this mean that the voltage drop across the PMOS-FET is only around 100mV+α?

Best regards,
Dice-K

0 Nini Zhong 27 days ago in reply to Dice-K

TI__Genius 13075 points

Hi Dice-K,

the ripple depends on Vin Vout and load current. The down mode enters when Vin< Vout _target -35mVand exits while Vout>Vout _target+100mV.

0 Dice-K 27 days ago in reply to Nini Zhong

Mastermind 7460 points

Hi Nini,
Thank you for your reply.

What does "the ripple" mean?

Does "Down mode" involve first dropping the voltage using a PMOS-FET and then slightly boosting it?

Best regards,
Dice-K

0 Nini Zhong 27 days ago in reply to Dice-K

TI__Genius 13075 points

Hi Dice-K,

Ripple means output voltage ripple. Please refer to this figure to compare the difference between down mode and boost .

Also app note inUltra-low Voltage (150 mV) Start-up Design Based on TPS61299 to see details about down mode and boost. Slightly distinguish from LDO.

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TPS61299: Down Mode