UCC28C56H-Q1: UCC28C56EVM

Hi Yakshraj,

Thanks for reaching out.

Yakshraj Sharma said:

A. Can I use this flyback control IC for both designs? If not, could you please suggest suitable alternatives?

Yes.

Yakshraj Sharma said:

B. If I want to commonize both designs on a single PCB, is it possible by changing only the transformer (turns ratio), or are there other major changes I should take into account?

As mentioned in the datasheet, table 9-1 (page 27/54), the converter can be designed for a wide Vin range. So, the same circuit should work for your application.

Yakshraj Sharma said:

C. I need to understand the high-voltage startup for VDD. Specifically:

• Why are two N-MOSFETs used and how are they controlled?

• How is the controller’s VDD voltage maintained during operation — is it always supplied from the auxiliary winding or can it be sustained from VIN?

The HV Startup circuit utilizes two 600-V depletion mode MOSFETs (Q1, Q2). The depletion mode MOSFET conducts when no gate voltage is applied and begins to turn off as the VGS voltage becomes more and more negative. It is completely off when VGS is below the turn-off threshold. The characteristics of the depletion mode FET make it well suited to implementing a current source for high-voltage startup. It is difficult to find a low-cost and small-size depletion MOSFET with 1.2-kV rating, but there are wide variety of selection in 600-V to 800-V domain. Therefore, the stacked depletion MOSFET configuration with the proposed gate clamp circuit will evenly distribute the voltage stress from the 1-kV input voltage.

During high-voltage (HV) startup from VIN, capacitor C12 must hold the VDD voltage above the UVLO turn-off threshold until the AUX voltage rises high enough to forward bias D12. If the value of C12 is not high enough the VDD voltage will decay below the UVLO turn-off threshold and the converter will prematurely stop switching. The controller will continuously cycle on-and-off as the VDD voltage transitions between UVLO turn-on and UVLO turn-off. One of the most common issues seen with new designs is the VDD capacitor value is too low and “there's no output voltage” or "it's not starting" is reported. The electrolytic bulk capacitor (C12) should be located relatively close to the VDD pin. On the other hand, the high-frequency bypass capacitor, C18, must be a ceramic type and be physically placed and grounded as close as possible to the VDD pin. A 1.0 μF, X7R capacitor is recommended for the high-frequency decoupling. To offset the effects of DC-bias, this capacitor must be rated to about 2x the expected VDD voltage (≥35V)

Please feel free to refer to the doc below:

https://www.ti.com/lit/pdf/sluaal3

Yakshraj Sharma said:

D. Could you also explain the role of the leading-edge blanking (LEB) circuit used in this schematic?

The role of LEB circuit is just to add additional delay to the CS pin like a deglitch time to make sure that short transients on the CS are not triggering and over current event shutting down the PWM controller. Hence, this additional circuit (RC time constant) acts like a deglitch filter to that pin.

Hope this helps. Please click on the green button if this resolves the issue, if not feel free to ask more.

Best,

Pratik A.

Hi Yakshraj,

Yakshraj Sharma said:

How to correctly size and calculate the transformer parameters when an auxiliary winding is used for PSR.

Please refer to this app note

https://www.ti.com/lit/pdf/slup416

Those values have been calculated for this application based on the voltage and power requirements, those are assumed values for the datasheet, for your application please calculate them.

Best,

Pratik A.

Hi Yakshraj,

Understand. My calculated value is the same as yours, please consider it a typo.

Best,

Pratik A.