TPS62067-Q1: TPS62067-Q1 stability analysis

Hello Sundy,

1) As mentioned in the datahsheet, it should not exceed the recommended effective Cout mentioned in D/S: if it is exceeded, please make sure loop stability has been analyzed. section 10.2.2.3 explains that, you need to test SW node, inductor current, output ripple and load transient to see that there is no jitter issue or oscillation in inductor current.

Looking that bode plot only, bode plot looks stable. But I will need other data also to see that loop is stable.

2) Section 4 of following app note explains the ferrite bead section guide:

https://www.ti.com/lit/an/slvafd4/slvafd4.pdf

3) With TPS62065-Q1, there will be no power good feature also. 

Thanks,

Farheen

Hello  Farheen，

Thanks for your reply.

And i am not clearly understand the effective Cout mentioned in D/S,  does it mean the sum of the capacitance at the buck output plus all the capacitance at the load side behind the ferrite beads?

I have read “slva441-optimizing tps6206x external component selection” application report.

In the case of using Cff compensation, the article states that with a 1uH inductor, the capacitor can be increased up to 47uF and the system will remain stable. However, in my design, when adding the three 22uF capacitors at the load end, the total capacitance value has exceeded the 47uF described in the application report. Is it still possible for the system to be in an absolutely stable state, considering that the compensation has already been designed internally?

Hello  Sundy,

This table is taken from which source?

Effective capacitance that is near to load before the ferrite bead. (value of capacitance after derating and tolerance, e.g. 22uF cap in general will have 15-18uF capacitance as effective value). I will still recommend checking duty cycle, load transient data to make sure that loop is stable. 

With Cff, do you know what value customer is using?  Are they using this formulae mentioned in datasheet:

Thanks,

Farheen

Hello Farheen,

   1. the table from SLVA441.pdf,  The document describes non-automotive-grade version. Is this document applicable to TPS6206X-Q1 devices?

   2. You mentioned that the capacitor before the ferrite bead is considered as "effective capacitance" while that behind the ferrite bead is not. However, from simple simulations, it appears that the capacitance behind the ferrite bead actually needs to be partially included in the calculation of effective capacitance. This is because the load capacitance (Cload) will form the first-stage corner frequency together with the output capacitance (Cout) and inductor (L), as shown in the figure below.

The corner frequency of a 1μH inductor and a 10μF capacitor is 50kHz (as the recommended design in the datasheet). But after adding the ferrite bead and C2(Cload), the first-stage corner frequency shifts to 35kHz. My key point here is: the addition of ferrite beads and large load capacitors at the load end causes the first-stage corner frequency to shift toward lower frequency. Since the datasheet specifies that the internally compensated LC corner frequency is 50kHz and the zero of the Cff compensation is at 25kHz, won’t the shifted position of the new LC corner frequency lead to system instability?

Considering the issue described above, can I still use relatively large capacitors for Cload here? Or should I follow the datasheet’s recommendation—where the maximum effective capacitance is 22μF—by setting Cout = 10μF and then 4μF for each Cload across the three load terminals, ensuring the total capacitance does not exceed 22μF?

TPS62067-Q1: TPS62067-Q1: Stability question - Power management forum - Power management - TI E2E support forums

3. Does the design value of Cff have to be determined strictly according to the 25kHz zero condition described in the datasheet? Or can it be adjusted based on the actual position of the LC corner frequency?

4. If conducting a load transient test, what is an appropriate value to set for the load current slew rate?

Hello Sundy,

1) Yes if BOM is same, then this documents should be valid also for automotive version.

2) Having a ferrite bead is not a requirement from device, so second stage filter capacitor and inductor is not included in BOM limits. But of course, as you said, if you use second stage filter, it will affect the transfer function. Coming to use of large capacitance, If effective capacitance is less than 47uF then it should be fine. If you use 3x22uF, what are the part numbers? So you can check the derating, if it is around 47uF then it should be fine.

3) Equation for Cff is for the customer guide for the recommended BOM. I will recommend to verify the stability with bench measurement.

4) You can test with load step from 0--> Max load current that this device will draw on customer board and slew rate also depends on customer chip. From my side, I will recommend to check with 1A/us.

For all this, as I said before, I will recommend to check with bench measurements.

Thanks,

Farheen