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TPS48111Q1EVM: Does TPS48111 charge-pump undervoltage flag reliably indicate MOSFET V_GS undervoltage, or should I add separate V_GS sensing?

Michelle Mathew
Intellectual 320 points

Part Number: TPS48111Q1EVM

Tool/software:

I’m planning to use TPS48111 in a high-side configuration. The device has a charge-pump undervoltage (CPUV) flag.

My question:

  • Does CPUV directly mean the MOSFET’s V_GS is below the safe threshold, or does it only reflect the charge-pump rail being low?

  • Are there scenarios where CPUV is OK but actual V_GS is still insufficient?

  • For automotive use, is CPUV generally sufficient, or would you recommend adding direct V_GS sensing (gate-to-source measurement) for robustness?

  • 0
    TI__Genius 12090 points

    Hi Michelle, 

    The device does not directly report a charge pump UVLO. 

    The UVLO is specific to the BST-SRC voltage, not necessarily VGS. 

    Generally the device features a strong PU current coupled with sufficient boot strap capacitance you should have no issues keeping VGS high. 

    Thanks, 

    Sarah

  • 0 in reply to Sarah Raines
    Intellectual 320 points

    Hi Sarah,

    Thank you for the response.

    In the event that a charge pump undervoltage does occur, is there any protection or fault indication by the IC.

    Or will the response of the IC be to turn OFF the FETs without signaling any fault, if charge pump undervoltage is detected. And if that is the case, will it auto-retry to turn ON the FETs. Or will we have to take action from our side to turn the FETs back ON and what would that action be.

    Thanks,

    Michelle

  • 0 in reply to Michelle Mathew
    TI__Genius 12090 points

    Hi Michelle, 

    There is no direct FLt indicator for this. The Gate will not be able to turn on. But will continue to "try" so long as INP is high and no other FLT occurs forcing PD to pull to SRC.

    Typically I would not expect a charge pump UVLO to be a coincidental or temporary phenomenon. This typically only occurs if you have an improper SRC connection or an inappropriately sized CBST. 

    Thanks,

    Sarah

  • 0 in reply to Sarah Raines
    Intellectual 320 points

    Hi Sarah,

    Thank you for the reply.

    Just needed some clarification,

    My understanding is that once the charge pump voltage falls below the Charge pump UVLOR value of 7.5V while operation, the gate will be pulled down to source voltage. Suppose the charge pump voltage fell to 7V, the charge pump wont attempt to turn ON the FETs with the available V_GS of 7V, causing the FETs to operate in a high RDS_ON region. It will simply not turn ON the gate at all. 

    Please let me know if the actual working is any different from what I have described here.

    Regards,

    Michelle Mathew

  • 0 in reply to Michelle Mathew
    TI__Genius 12090 points

    Hi Michelle, 

    Below the charge pump UVLOF value the the gate driver logic is disabled. For initial turn on the EN pin activates the charge pump, which will begin charging BST-SRC. Above UVLOR the gate driver logic is enabled. At this point INP HIGH will attempt to turn on the FET. If the BST-SRC voltage falls to UVLOF the gate driver logic will once again be disabled. Here the FET will remain pulled down even if INP is HIGH. 

    Between UVLOR and the ~10V charge pump turn off region the FET can operate in a high RDSON region, but the expectation is this would be very brief "on its way" to adequate BST-SRC voltage. 

    Thanks, 

    Sarah