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BQ40Z50: BQ40Z50-SCD protection delay issue

liu billy
Intellectual 570 points
Part Number: BQ40Z50

Tool/software:

hello ,

     The BQ40Z50-SCD protection delay issue,We have registered the values ASCD1: F5 and ASCD2:47 in the program, corresponding to delays of 244uS and 915uS, respectively. The actual tested delay ranges are 1220uS and 416uS.
If the actual test exceeds the upper limit of the ± 10% error range specified in the specification sheet, please help explain the reason.

  • 0
    TI__Mastermind 25855 points

    Hello,

    This question has been assigned and will be reviewed when possible, in the meantime please attach associated .gg/.log files.

    Thank you,
    Alan

  • 0
    TI__Intellectual 902 points

    Hello Liu,

    There is current fault detect time, so the total time would be SCD Delay (244 us) +/- 10% error + Tdetect (160us) = ~406us

    When we characterize the timing requirements on the lab, we measure internal signals which might not take into account the rise and fall time of the FETs gates.

    For example, it might take 915us +/- 10% for the DSG Gate to start falling, but it doesn't mean it will instantly go to zero.

    The FETs gates have capacitance that depends from FET to FET. 

    -Miguel