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LM5017: Problems with chip testing

Tonyx.wu
Genius 4015 points
Part Number: LM5017

Tool/software:

Summary of LM5017MRX/NOPB issues：

Application：

Household storage drive auxiliary power source, input voltage 21-46.5V, one winding on the primary side outputs 10.5V load 300mA, two windings on the secondary side each output 10.5V load 40mA.

  1. LM5017 Bootstrap capacitor：

In the application circuit, the specification of the BST capacitor is 0.01uF. Based on our previous application experience, we have adjusted the capacitor to 100nF.。

 

Question

  • What considerations are behind setting 10nF? Does adjusting the capacitor to 100nF have any impact on the internal circuit
  • Could you provide the inrush current capacity of the internal BST diode at 100℃
  • Is there a current-limiting resistor inside the BST capacitor charging circuit? If so, what is it？

When the BST voltage of the self-lifting capacitor 100nF was established to 7.6V upon startup, there was no impulse. At the moment of wave generation, there was an impulse current of approximately 38mA (impulse current during wave generation upon startup), as shown in the following figure.

 

The BST voltage follows the external Vcc voltage. When starting up and generating waves, when the second wave begins and the external voltage exceeds the internal LDO output of 7.6V, an inrush current will be generated, which will impact the internal BST.

2.Voltage stress of SW-RTN

Question

  • The stress parameter in the SW-RTN specification sheet is Vin+0.3V. What considerations are behind 0.3V? Is it out of concern that the upper body diode may be damaged by a large current in a short time, or are there other components inside that cannot withstand the high voltage? Is Vin Max=100V or the actual input voltage?
  • For SW-RTN, we detected a Spike of Vin+1V (Vin=13.2V) under light load. By increasing the Vin voltage, the Spike rose to Vin+2V (Vin= 25V). Help assess whether there is any risk in this.

 

The conduction voltage drop of the upper body diode will clamp the SW-RTN to Vin+0.3V. Therefore, the specification sheet provides a theoretical clamping value and does not necessarily have to be lower than this value.。

3.SW-VIN voltage stress

Question

 

Does the SW-Vin specification (upper MOS stress) need to be reviewed in reference to SW-RTN?

 

We test ourselves to have a negative Spike of -2.1V@73ns and a positive Spike of +1.4V@87ns. Help assess whether there is any risk in this positive or negative specification of SW-Vin and how it is considered。

  • 0
    TI__Guru 59121 points

    Hello Tony 

    • What considerations are behind setting 10nF? Does adjusting the capacitor to 100nF have any impact on the internal circuit ==> CBOOT should be ~ 10 times larger than CVCC. Also, should be enough big to make V(BOOT-SW) drop small less than ~0.3V. 
    • Could you provide the inrush current capacity of the internal BST diode at 100℃ ==>  Need a time to get the answer. 
    • Is there a current-limiting resistor inside the BST capacitor charging circuit? If so, what is it？ ==> No we don't have. But, the diode itself has a parasitic resistance. 
    • The stress parameter in the SW-RTN specification sheet is Vin+0.3V. What considerations are behind 0.3V? Is it out of concern that the upper body diode may be damaged by a large current in a short time, or are there other components inside that cannot withstand the high voltage? ==> Both 
    • Is Vin Max=100V or the actual input voltage? ==> 100V is the Abs Max. V(VIN-RTN) should be always less than or equal to 100V.  
    • For SW-RTN, we detected a Spike of Vin+1V (Vin=13.2V) under light load. By increasing the Vin voltage, the Spike rose to Vin+2V (Vin= 25V). Help assess whether there is any risk in this.==> I cannot guarantee anything outside of datasheet.  
    • Does the SW-Vin specification (upper MOS stress) need to be reviewed in reference to SW-RTN? ==> Yes

    -EL 

  • 0 in reply to EricLee
    TI__Guru 59121 points

    Hello Tony

    Typically the diode can handle about 1A, but I cannot guarantee anything outside of the datasheet. 

    -EL

  • 0 in reply to EricLee
    Genius 4015 points

    1.What considerations are behind setting 10nF? Does adjusting the capacitor to 100nF have any impact on the internal circuit ==> CBOOT should be ~ 10 times larger than CVCC. Also, should be enough big to make V(BOOT-SW) drop small less than ~0.3V. 

    -- It should be that CvcC is ten times Cboot.  It needs to be large enough to ensure that the voltage drop is less than 0.3V.  Does this mean that as long as the voltage drop is less than 0.3V, the capacitor does not have to be exactly the capacitance value specified in the specification sheet?

    2.Is Vin Max=100V or the actual input voltage? ==> 100V is the Abs Max V(VIN-RTN) should be always less than or equal to 100V.

    Is the Vin in the requirement of sW-RTN being less than Vin + 0.3V in the specification sheet the actual input voltage or 100V?  Or does it mean that as long as sW-RTN is less than 100V - 0.3V, it is fine, without having to be the actual input voltage minus 0.3V?

  • 0 in reply to Tonyx.wu
    TI__Guru 59121 points

    Hello Tonyx

    Does this mean that as long as the voltage drop is less than 0.3V, the capacitor does not have to be exactly the capacitance value specified in the specification sheet ==> That's a general guideline. I recommend you to use 10nF if no special reason to use other value since the device is validated with 10nF CBOOT. 

    Or does it mean that as long as SW-RTN is less than 100V - 0.3V, it is fine, without having to be the actual input voltage minus 0.3V==> It means V(VIN-RTN) +0.3V should be always greater than V(SW-RTN).

    -EL