TPS54310 Package

The TPS54310 only comes in one package, 20 pin PWP.  I think you may be referring to the power dissipation rating, which shows for both powerpad soldered to the PCB and not soldered.  I would ignore the "not soldered".  I highly recommend that you solder the powerpad to the PCB for optimum performance.

Application Report SLVA109 -December 2001 on Designing with the TPS54310 synchronous Buck Regulator, gives one formula for the calcuation of resistor R5 as shown in Figure 1 Typical Schematic.  We are using the same schematics.  What we are not sure while calcuating the value of R5 is which value should be taken for COUT in the Equation 13.  It states COUT is teh capacitance of a single output capacitor.  Where this capacitor COUT?  Does it mean the PCB trace capacitance or something in the same circuit itself? Please clarify.

Thank you,

-Krishna.

Thank you John Tucker.

I have another request: 

We need the following three regulators for designing a board:

1. 3.3V/7A regulator
2. 0.9V(preferably) or 1V/12.105A
3. 1.1V/14.28A

All the above three voltage levels have to be derived from +5V supply (made available by +5V adapter)

Please suggest some best performing/most sought after regulators for this spec from TI product line.

Thanks

Krishna.

You might want to start a new thread for this.  For the 3.3 V rail, you could possibly us TPS54810 or TPS54821.  The other higher current supplies will probably be best designed using controllers with external FETs.  I do not directly support those parts.  You could use TIs "Power Quick Search"  to find suitable ICs.  If you start a new thread with a suitable title, you can attract other experts to give advice.

Thank you very much John Tucker for your support and advice.

Created a thread as per your advice.

thanks

-krishna.

This refers to TPS54310QPWPRQ1 DC/DC converter.  What are the benefits or advantages of having SS/ENA (Slow-Start) Enable feature with regard to applicaions.?  Is it like they can be used for power sequencing? why should it be that the output voltage is disabled(or the device is in shutdown state) until the output reaches the specified value? Please explain.  If I use this for my on-board power regulator, I shoud expect a delay of at least 3.78 ms to get regulated output ( I can call it as latency!).  Or, is it OK to get away with the Css capacitor all the way by simply keeping the SS/ENA pin open by removing Css cap.  Please clarify.

Thank you,

Best Regards,

Krishna.

Thanks John!

My understanding is that the delay in building up of the output voltage is intentionally introduced in the system. Am I correct?

1.  I would like to know what is the benefit of slow-start with regard to application?

2.  What is the impact of slow-start time other than meeting the rise time requirements?

3.  If we keep the SS/ENA pin open without connecting a capacitor, will it still work?

4.  I understand from your reply that it has a minimum of start up time of 3.35ms when we dont connect a capacitor across SS/ENA pin. Is my understanding right.?

Please explain.

Thank you very much John.

Best Regards,

Krishna.

1.  Slow start controls the rate at which the output voltage ramps up from 0 V to the regulated output.  If it is not controlled by such a mechanism it may have non-monotonic start up or over-shoot and ringing at start up.  Additionally it serves to limit the inrush currents  and allows the output capacitors to be charged with a constant current.  Also, you may have timing constraints based on your load circuits and other voltage rails in your system.

2.  The slow start time sets the charge current for the output caps.  In the simplest terms, the output current at start up = I load + (Cout * Vout / Tss).  This should not  exceed the current limit of the device.

3.  Yes,just make sure your output capacitance is not too large (see above)

4.  No it has a "typical" slow start time of 3.35 msec.  The other specifications are in the datasheet