Tool/software:
Hi,
I am designing an LDO power supply with the TPS74801DRCR and I would like your opinion on a VBAIS violation I have.
My design:
VIN = 5V+/-5%
Vbias tie to VIN
VOUT = 3.3V +/- 3%
Iout max = 0.3A
Table 7-1 in the datasheet says for normal mode “VBIAS ≥ VOUT + 1.6 V”. But since my VIN can be -5%:
4.75 ≥ 3.3+1.6 is not valid, it is a violation.
Looking at the VBIAS dropout voltage in section 6.5, the test condition is at Iout = 1.5A
From the different graphs in the datasheet, like Figure 6-32, it looks like the VBIAS dropout voltage requirement is lower if Iout is lower.
How do you feel about my parameters above and to violate the “VBIAS ≥ VOUT + 1.6 V” since my Iout is low ?
Would that still be a reliable design?
Thanks.
