TPS65224-Q1: ADC acquisition issue

Part Number: TPS65224-Q1
Other Parts Discussed in Thread: TPS65224, AM62A7

Tool/software:

Hello, engineers 

 When we used GPIO5 of the TPS65224 to perform ADC acquisition, we found that the ADC acquisition port of the chip would automatically enable a pull-down resistor by default. This caused the ADC voltage division value to decrease in a stepped manner when we were collecting the voltage. Moreover, the higher the collected voltage, the greater the voltage drop. We attempted to modify the bit 3 of the GPIO5 register to disable the pull-up resistor, but it had no effect. Only when setting GPIO5 bits 6 and 5 to GPIO mode did it work.

Could you please tell me if there is any other way to close this dropdown menu?

The figure below shows the change in the AD voltage divider value after I enabled the ADC acquisition.

At this moment, my collected voltage is 32.5V, and the voltage is divided by 100K and 10K resistors.

Thanks,

xiwen

  • Hi Xiwen,

    I would like to know the full OPN (orderable part number) for further investigation. If you don't know this you can read registers 0x1, 0x2 and 0x3. Since you have the input voltage to the GPIO5 (ADC) higher than 1.2V you probably have the internal resistive divider enabled. One thing to note is that the GPIO5 is in LDOVINT domain which is 1.8V so when the voltage at the GPIO5 goes above this it starts to leak thus increasing current. This could be one reason for your drop.

    regards,

    Niko

  • Hi,Niko

    The complete order code for the chip is TPS6522430RAHRQ1, which is compatible with SOC AM62A7.

    I configured the internal voltage divider ADC_RDIV_EN=1 in the register, so voltages above 1.2V can be supported for sampling.

    Thanks,

    Xiwen