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UCC21750-Q1: External Soft turn-off capacitor calculation

Prathik P
Prodigy 90 points
Part Number: UCC21750-Q1
Other Parts Discussed in Thread: UCC21750

Tool/software:

Hi,

I want to use the UCC21750 with an external totem pole buffer to drive a SiC power module (CAB6R0A23GM4T) at 25kHz. In section 9.2.2.8 of the gate driver IC, the following output buffer and external STO circuit are shown:

An RC circuit consisting of Csto and Rsto are used to achieve soft turn-off. The calculation of Rsto is pretty clear from the datasheet, but I need help with the calculation of Csto.

To calculate Csto, the soft turn-off time Tsto must be known. How do I determine or calculate this value for my application? (Note: Vdd = 15V, Vee = -4V)

Also, I would like to understand why the OUTH and OUTL gate driver pins are tied together? By not tying them together, the Rsto resistor can be eliminated. I don't know if I'm missing something, but I can't really think of a reason why tying the two would be beneficial.

  • 0
    TI__Intellectual 1216 points

    Hello Prathik,

    Thanks for reaching out.

    tSTO is your desired timing for soft turn-off the SiC MOSFET. To calculate CSTO, you can use the UCC217xx Calculator Tool on the UCC21750 product page within the Design and Development section. I have attached the link below.

    UCC21750 data sheet, product information and support | TI.com

    OUTH is the gate "pullup" to VDD, and OUTL is the pulldown to VEE. When PWM input is HIGH, there are internal FETs which turn on to charge the IGBT/FET gate up to VDD. When PWM goes low, OUTH becomes High-z and OUTL FETs turn on, pulling the gate low down to VEE. Thses two pins are tied together to behave like a single low impedance output node. If OUTH and OUTL weren't tied together, the circuit would have asymmetric drive paths which could lead to uneven switching behavior and longer propagation delays. Separating them would also not eliminate the need for Rsto, as you need it to limit the inrush current to below the current rating of the internal FET.

    I hope this helps.

    Best regards,

    Muiz.

  • 0 in reply to Muiz Ishola
    Prodigy 90 points

    Hi Muiz,

    I think your response to my second question is clear. 

    My first question is actually about how the value of tSTO is determined. The excel tool which you have asked me to refer helps me calculate CSTO for a known value of tSTO, but my question is how do I determine what value for tSTO is suitable for my power module? Do you have some guidelines to determine what the value of tSTO should be?

    And apart from this, I do not see a tab in the excel tool to calculate the resistance in series with the base of the totempole BJTs. Do you have any calculation formulations for that?

    Regards,

    Prathik

  • 0 in reply to Prathik P
    TI__Intellectual 1216 points

    Hi Prathik,

    Finding the tSTO value is not as straightforward as just plugging numbers into a formula since its application dependent. The idea is to choose a soft turn-off time that's long enough to limit the di/dt during during a short-circuit event (this controls the VDS overshoot), but still short enough to ensure that the device remains within it's short-circuit withstand time.

    Regarding the resistance in series, RG_Int is the internal resistance of the SiC MOSFET or IGBT module while RG_1 is the gate resistance. The resistor value for RG_Int is dependent on your SiC MOSFET or IGBT and the RG_1 resistor value is dependent on what you want the gate drive current to be.

    Best regards,

    Muiz

  • 0 in reply to Muiz Ishola
    Prodigy 90 points

    Hi Muiz,

    So if I understand correctly, what you are saying is that I won't need a resistance in series with the base of the BJTs because the driver's internal resistance is sufficient to limit the base current of the BJTs to a suitable value?

    Prathik

  • 0 in reply to Prathik P
    TI__Intellectual 1216 points

    Hi Prathik, 

    No, not exactly. RG_Int is your CAB6R0A23GM4T SiC Module's internal gate resistance. From the module's datasheet, this value is 1.3 ohms.

    RG_1 is the gate resistor for the SiC Module. The RG_1 gate resistor limits the gate charge current and indirectly controls the IGBT collector voltage rise and fall times.

    You're still going to need to connect RG_1 to your SiC Module.

    Best regards,

    Muiz.

  • 0 in reply to Muiz Ishola
    Prodigy 90 points

    Hi Muiz,

    I think there is some confusion here. I am not asking about RG_1, the resistor in series with the gate of the power MOSFET being driven, or RG_int, the internal gate resistance of the power MOSFET being driven.

    My question is about the resistance in series with the base of the BJT buffer, which is typically used to limit the current going into the base of the BJT. Since the BJTs amplify current, there is generally no need to connect the base of the BJTs directly to the OUTH and OUTL pins. I was asking if TI advises connecting the OUTH and OUTL pins directly to the base of the BJT or use a current limiting resistor?

    In addition to this, the capacitor Csto and resistor Rsto result in an increased power consumption during normal operation. Since Rsto is very small, the driver IC is supplying a huge amount of current into Csto as if it is driving the gate of another MOSFET. This is going to significantly increase the power drawn from the power supply, especially since Csto is in the order of 10-20nF, depending on the timing. Is this the best approach to enable STO with an external buffer?

    Regards,

    Prathik

  • 0 in reply to Prathik P
    TI__Intellectual 1216 points

    Hello Prathik,

    Apologies for the confusion. TI recommends using a current limiting resistor to connect the OUTH and OUTL pins to the base of the BJT. Regarding enabling STO with an external buffer, the external components must be added to implement STO instead of normal turn off speed when an external buffer is used.

    Best regards,

    Muiz.