TPS61088: TPS61088 (RHL package) — EN low does not collapse VOUT; output remains at 4.5 V without discharge

Tool/software:

Hello TI Support,

We are using the TPS61088RHLR as a boost regulator to generate 4.5 V from a Li-ion battery (VBAT 3.0–4.2 V). With EN driven low, we expect the output to be disabled; however, the 4.5 V rail remains at approximately 4.5 V after deasserting EN. There is no obvious output discharge observed.

Design details (see attached schematic excerpt):

• Device: TPS61088RHLR

• VIN: single-cell Li-Po (3.7–4.2 V), input capacitors 2×10 µF + 0.1 µF close to VIN

• Inductor: 470 nH

• VOUT set to 4.5 V via R10 = 182 kΩ, R13 = 66.5 kΩ

• Output caps: C17 = 47 µF, C22 = 47 µF (low-ESR ceramics)

• SS: C19 = 8.2 nF

• COMP network: R16 = 23.7 kΩ, C20 = 560 pF, C21 = 36 pF

• ILIM: R18 = 105 kΩ

• MODE pin is currently unconnected in this revision (floating)

• EN is driven by a GPIO; EN low is measured at the pin at ~0.02 V

Observed behavior:

• Pulling EN low stops switching on the SW node (verified on oscilloscope).

• Despite that, VOUT remains at ~4.5 V for an extended period. With no intentional load, the rail does not visibly decay within our test window.

• With certain downstream loads connected, VOUT can remain at ~4.5 V even with a bleeder; we suspect reverse current/back-feed through the load into VOUT.

Questions:

1. Does TPS61088 provide any internal output-discharge or load-disconnect function when EN = low? The datasheet indicates shutdown and low IQ, but does not explicitly state an output discharge path.

2. With MODE floating, could internal biasing cause unintended behavior during shutdown (e.g., leakage paths or partial bias keeping VOUT latched)? Would TI recommend tying MODE explicitly to GND (PFM) or VIN (FPWM) for robust disable behavior?

3. What is the expected reverse conduction path from VOUT to VIN when the device is disabled? Is there a recommended external ideal-diode/load-switch arrangement if a true output disconnect is required?

4. Are there recommended values or placement notes for the EN pin RC filter to avoid coupling from the SW node?

5. Given our inductor (470 nH) and compensation values above, is there any device state during shutdown that could leave charge on the output caps longer than expected?

Reproduction steps:

1. Power the board from a bench supply set to 3.8 V at VIN.

2. Enable the converter; VOUT regulates at 4.5 V.

3. Pull EN low (measured 0.02 V at EN pin).

4. Observe: SW node activity ceases; VOUT remains ~4.5 V with no load.

We would appreciate confirmation of the shutdown behavior and guidance on implementing a true output-off condition (e.g., recommended load-switch/ideal-diode devices or an app note reference).

Thank you for your help.