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TPS552882-Q1: TPS552882QRPMRQ1 - query about EN/UVLO Pin

Part Number: TPS552882-Q1


Hi team,

we are having the following query regarding TPS552882QRPMRQ1:

  • We are using multiple regulators in a cascaded configuration, where the enable pin is controlled either by the power good signal of another regulator or by an MCU I/O. From the image in the datasheet, it appears that the I_UVLO_HYS current seems to flows into the EN/UVLO pin. Could there be any leakage from EN/UVLO pin through the pull-up resistor to the voltage rail or to the MCU pin connected. image.png
  • The regulator is going to be used in an automotive application, where it must operate during vehicle cranking, where the input voltage may drop to 3–4 V while the regulator maintaining a 5 V output. whether the output voltage is sufficient to keep the internal LDO operating correctly, and what the minimum output voltage required for the VCC LDO to remain powered for normal opeationimage.png 

Thanks,

Pream krishna.

  • Hi Pream,

    We will look into this and reply to you later.

    BRs,

    Bryce

  • Hi Pream,

    Thanks for your patience.

    Regarding to your questions:

    1. Yes, the leakage current could go through the pull-up resistor when EN pin is controlled by the PG signal or MCU pin rail.

    2. When Vin drops to 3-4V, the internal LDO will be supplied by 5VOUT, which is still sufficient. 

    BRs,

    Bryce

  • Hi Bryce,

    Thanks for the reply, 

    he leakage current could go through the pull-up resistor when EN pin is controlled by the PG signal or MCU pin rail
    1. From which voltage sources IUVLO_HYS? If the EN/UVLO pin is driven above V_UVLO, does that prevent leakage to the pull-up rail from EN/UVLO pin?

    When VIN is within its operating range, but EN is LOW, what is the Power Good pin state? Is PG asserted low (to GND) because VOUT is not active, or does PG remain high impedance?

    Thanks,

    Pream Krishna.

  • Hi Pream,

    1. The IUVLO_HYS is from internal VCC supply. The sourcing current from EN/UVLO pin is on when EN/UVLO pin is above VUVLO.

    2. If device is shutdown when EN is low, the Power Good pin is high impedance state.

    BRs,

    Bryce

  • Hi Bryce,

    Thanks for the reply.

    • It would be help if you could give more insights of usage of hysteresis current IUVLO_HYS, as we expect inputs to high impedance.
    • what is its current direction (as seen in Figure 7-1) with respect to EN/UVLO pin when regulator is enabled, standby mode and shutdown mode.
    • The datasheet is mentioning the terms as "from", "sourced out of" does that mean that current is being IUVLO_HYS is taken or sourced from EN/UVLO pin into the IC. if that's true how could the current leak into pulled up rail.

    Yes, the leakage current could go through the pull-up resistor when EN pin is controlled by the PG signal or MCU pin rail.
    •  Will the IUVLO_HYS will leakage into pull up resistor to source power rail even if the EN/UVLO is pulled up to 5V/3.3V.

    Thanks,

    Pream Krishna.

  • Hi Pream,

    I will reply to you tomorrow, thanks.

    BRs,

    Bryce

  • Hi Pream,

    1.The hysteresis current IUVLO_HYS is used to provide hysteresis that prevents on/off chattering in the presence of noise with a slowly changing input
    voltage.

    2.Only when IC is enabled, IUVLO_HYS will go through the pull-up resistor. In stand by and shutdown mode, it will not flow.

     Will the IUVLO_HYS will leakage into pull up resistor to source power rail even if the EN/UVLO is pulled up to 5V/3.3V.

    Yes.

    4. A 100k pull down resistor is also needed.

  • Hi Mulin,

    Thanks for the reply.