LM5060: No output from Gate during repeated power cycling

Thanks for reaching out. We will get back to you by Friday. 

Hi Avishek Pal,

We have customer meeting tomorrow morning. Could you please help to give your comments by EOD today? Thanks for your support.

Per my observation, 2 things are strange.

1) During power supply disconnected period, timer capacitor charging is triggered. Why?

The timing seems like after UVLO triggered and MOSFET's body diode conducted.

2)Why nPGD pin is high

Best regards,

Terry

Based on the analysis of the no-power issue during rapid power cycling, after changing PR214 from 100K to 39K, multiple tested boards have shown no recurrence of the failure. Please kindly confirm the following:

1. When the chip's EN pin voltage exceeds 2V (effective level), what should the corresponding voltage level be at its VIN (power supply) pin?

2. The chip's nominal operating voltage range is 5.5V to 65V. What are the risks if the EN signal is activated when the supply voltage is outside this specified range? What are the timing requirements between the VIN and EN pins for this chip?

Hi Avishek Pal,

Customer is pushing us. Could you please reply Jim's and my question by EOD today?

Regards,

Terry

Hi Avishek,

Could you help to check this question? thanks.

Hi Avishek,

Any update for this issue? 

Hi Avishek,

Please help to reply to below 2questions. 

Che Wen Yeh said:

• When the chip's EN pin voltage exceeds 2V (effective level), what should the corresponding voltage level be at its VIN (power supply) pin?

• The chip's nominal operating voltage range is 5.5V to 65V. What are the risks if the EN signal is activated when the supply voltage is outside this specified range? What are the timing requirements between the VIN and EN pins for this chip?