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TPS55289-Q1: Questions about TPS55289-Q1 operation and characteristics

Part Number: TPS55289-Q1

Hello TI Team,

I am currently evaluating the TPS55289-Q1 for use as a USB PD power source, and I would like to confirm several points regarding its operation and characteristics.
Could you please help clarify the following items?


Q1. Enable pin timing
After the EN pin is pulled high, how long does it take before I²C communication and other device functions become available?


Q2. Soft-start behavior
In Section 5.5 Electrical Characteristics, does the parameter “Soft-start time” refer to the startup time of the internal reference voltage?
Also, is my understanding correct that the actual VOUT ramp-up time depends on the slew rate value configured in the VOUT_SR register?

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Q3. Overcurrent protection
If Current_Limit_EN is disabled, will the inductor current limit function also be disabled?


Q4. Switching frequency tolerance
Regarding the switching frequency parameter in Section 5.5 Electrical Characteristics,
is it correct to understand that the ±10% variation does not include the external resistor tolerance?
Also, should the design ensure that the actual frequency, including all variations, does not exceed 2.2 MHz?

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Thank you very much for your support.
Best regards,

  • Hi Hiroki,

    Thanks for reaching out. I will look into the questions and reply to you next Monday.

    BRs,

    Bryce

  • Hi Hiroki,

    Please see below my reply:

    Q1- I²C communication and other device functions become available after VCC is high, not the enable is high.

    Q2- Yes, your understanding is right.

    Q3-No, current_Limit_EN is for output current limit control. It is not the inductor current limit. Please look below spec:

    Q4- usually the Switching frequency variation is small and we can regard the frequency setting is correct.  But tolerance of 10% can be guaranteed, if the actual Fsw exceed to 2.2Mhz, it is also fine, and no risk.

    Thanks,

    COlin

  • Hi Colin,

    Thank you for your reply.

    I would like to confirm one point regarding Q1.
    In Sections 6.3.5 and 6.3.6 of the datasheet, it is described that the I²C communication and other device functions become available when the VIN and EN/UVLO pin voltages exceed their UVLO thresholds (VIN > 3 V and EN/UVLO > 1.23 V).

    However, in your reply, you mentioned that the I²C communication becomes available after VCC is high.
    Could you please clarify which condition actually enables I²C communication when VCC becomes high, or when VIN and EN/UVLO exceed their UVLO thresholds?

    Best regards,
    Hiroki

  • Yes, VCC will be high after VIN and EN exceed their UVLO thregholds. Then I2C will be accessible.

  • Hi Colin,

    Thank you for the clarification. That makes sense.

    As a follow-up question:
    When VIN = 24 V and a 4.7 µF bypass capacitor is connected to the VCC pin,
    could you please tell me the approximate time it takes for the VCC voltage to rise after the EN pin is pulled high?

    Also, is there any recommended delay time before the host MCU starts I²C communication after asserting EN?

    Best regards,
    Hiroki

  • Hi Hiroki,

    I cannot guarantee th eapproximate time, becasue of this is not specfied in datasheet..

    Usually 1ms is a recommended time for I2C communication after VIN and EN beyond UVLO threadhold.

    Thanks,

    Colin