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UCC28180: Design review (UCC28180 and UCC28951)

Jia-Wei Seah
Prodigy 55 points

Part Number: UCC28180
Other Parts Discussed in Thread: UCC28951, , UCC27714EVM-551

Hi,

I am creating a AC/DC power supply module taking in line voltage 230Vac A 50/60Hz and outputting 48Vdc/10A continuous. The high level architecture is "Line input (with some protection and EMI filtering) -> Power Factor Correction circuit (UCC28180) -> Phase-Shifted Full Bridge circuit (UCC28951) -> Output".

I do not have the schematics done yet, but I have based my design on UCC28180EVM-573 and UCC27714EVM-551 (this EVM uses UCC28951). I have attached both EVM pdf files. Inside those files at the EVM schematic page, you will find the EVM schematics with annotations on the components that we have selected to meet our design requirements. The selection of components is supported by "UCC28180 Design Calculator Tool: SLUC506" and "UCC28951 Excel Design Tool: SLUC222E" which I have also attached.

I would like to request your assistance in reviewing the excel design calculators and our selection of components and feedback if you noticed any issues or any blind spots that we may have missed. The schematics that we want will largely reference the EVM.

I have also attached a "Design Requirement" word file that summarizes all the design requirements that we are trying to meet. If additional information is needed, feel free to ask!

Design Requirements.docx SLUC222E_10A.xlsx [User's Guide] sluub02a.pdf sluc506c_10A.xls [User's Guide] sluuat3b.pdf 

  • 0
    TI__Prodigy 580 points

    Hi Seah,

    I had a look at your design. The inductor value is slightly larger because as I understand you are trying to design for high line applications (190Vrms to 254Vrms input).

    If at all you want to reduce the size of the inductor you can choose slightly higher ripple. If size of inductor is not a constraint, you can go ahead with the same inductor value as calculated by excel calculator.

    Also, please use the values of RVCOMP and CVCOMP as recommended by excel calculator. I am putting a snippet for the same below:

    I request you to open an another thread for UCC28951 design review.

    Regards

    Sagar

  • 0 in reply to Sagar Rothe
    Prodigy 55 points

    Hi Sagar,

    Thanks for your prompt review and feedback. Noted on your points regarding RVCOMP and CVCOMP, I will have a look at that.

    Regarding your suggestion about the inductor, it is indeed very large in size. With your suggestion, we have opted for something reasonably smaller that still meets the electrical requirements calculated in the excel (MPN: PFC183209B-821K). I have attached the datasheet /cfs-file/__key/communityserver-discussions-components-files/196/_5B00_Ind_5D00_-PFC183209B_2D00_821K.pdf, do share your feedback. Referring to the "Design Requirements" word file previously attached, we are targeting 20% inductor pk-to-pk current ripple factor as we have rather strict load step response (+/-600mV) and noise/ripple requirements (165mVrms and 500mVpk). Therefore, there is a concern if a larger ripple factor will cause an impact in the output signal.

    For the input EMI, we did a slight change from the EVM to have double the qty of CM chokes, Y-caps and X-Cap to meet the stringent EMC requirements in the word file. The schematic would look something like this, do you have any other recommendations?

    Besides this, do you see the need for snubber circuit at the QFET (labelled Q1 in EVM) and DBOOST (labelled D2 in EVM)? The UCC28180 switching frequency is set at 118kHz which is not particularly high. If yes, would you be able to share guidelines in determining the values.

    Also, do you see the need for a clamp diode on the ISENSE pin to GND (parallel to CISENSE)? It is not present in the EVM or excel calculator but certain application notes do suggests.

    Noted on your request to open a separate thread for UCC28951 design review, I will do that. Thank you.

    Best regards,

    Jia-Wei

  • 0 in reply to Jia-Wei Seah
    TI__Prodigy 580 points

    Hi Jia-Wei,

    Given the target of 20% peak-to-peak inductor ripple, it is expected that the inductor size will increase. However, this is a perfectly acceptable trade-off if the requirements for ripple current and load step response are stringent, as a slightly larger inductor can help meet these demands.

    As per your EMI requirements, incorporating a two stage input EMI filter is a good idea and the provided schematic looks fine. 

    Since the inductor is slightly larger, I recommend to have a provision of snubber circuit to mitigate the voltage spikes and ringing to make the design more reliable.

    Regarding your question on clamp diode on ISENSE pin - Yes, there should be a clamping diode on ISENSE pin as recommended in data sheet. The voltage at ISENSE pin should be limited between 0V and -1.1V. Inrush currents at startup have potential to drive the ISENSE pin more negative, so a diode clamp is necessary at ISENSE pin. The forward voltage drop (Vf) of diode used should be greater than -0.438V (PCL threshold) and less than -1.1V. 

    Regards

    Sagar

  • 0 in reply to Sagar Rothe
    Prodigy 55 points

    Hi Sagar,

    Thanks for your recommendations.

    Referring to the previously attached two stage EMI filter circuit, as most of the normal practices are protection between L-N, do you see a need for L-G or G-N protection?

    Regarding the snubber circuit, do you have any recommendations on how to determine the suitable component values?

    Best regards,

    Jia-Wei

  • 0 in reply to Jia-Wei Seah
    TI__Prodigy 580 points

    Hi Jia-Wei,

    Yes, there's a need of L-G and G-N protection to filter out the common mode EMI. This is done by using the Y-caps which are present in your circuit already.

    In large sized inductor there will be turn to turn capacitance of the inductor which can also cause EMI problems and high dv/dt. If in case you want to use a snubber capacitor across FET for meeting EMI requirements, its better to just have a provision to place that capacitor across FET. The value of this capacitor will be based and depend your EMI performance and should be adjusted accordingly.  The snubber capacitor will help to slow down the dv/dt, however can increase the switching losses in the converter because the energy stored in the snubber cap will get dissipated during turn on of the FET.

    Unfortunately, I don't have a specific document related to snubber circuit design in general, but I am sure you will be able to find it on internet.

    Regards

    Sagar  

  • 0 in reply to Sagar Rothe
    Prodigy 55 points

    Hi Sagar,

    Thanks for the feedback. We will make some changes based on your recommendations.

    I have no further questions, thank you for reviewing the design.

    Best regards,

    Jia-Wei

  • 0 in reply to Jia-Wei Seah
    Prodigy 55 points

    Hi Sagar,

    I would like to check about the protection features of UCC28180. I noticed that there is soft-over current, peak current limit (cycle-by-cycle) and over/under voltage protection. Among these, only the PCL is labelled cycle-by-cycle. Does this mean that if I am setting UCC28180 switching frequency at 118kHz, the PCL detection time/window is 8.5us? What is the time from detection to disabling GATE pin? and does this mean that the SOC and OUVP does not have such a quick detection time since they are not cycle-by-cycle?

    Best regards,

    Jia-Wei

  • 0 in reply to Jia-Wei Seah
    TI__Prodigy 580 points

    Hi Jia-Wei,

    The PCL function is to help keep MOSFET or inductor safe without damage. The UCC28180 is a fixed-frequency controller and the GATE output is driven every switching cycle, whether the current exceeds PCL threshold or not. 

    Leading-edge blanking (LEB) is a common technique to prevent premature shutdown of PWM gate-drive pulses due to current spikes at the turn-on edge of the gate-drive.  These spikes come from discharge of switched-node capacitance and output-diode reverse recovery (if any) at the turn-on edge of the MOSFET conduction.  The spikes often exceed the PCL level, but go away before the 300ns blanking time expires. 
    That way, turn-on spikes will not interfere with normal peak current protection of the inductor current in each switching cycle.

    If the inductor current remains above the PCL threshold after the 300ns blank time expires, then GATE is shut off immediately.  But turn-off delays due to discharge time of MOSFET gate-source capacitance and Vds charge-up time of MOSFET Coss can allow inductor current to rise higher than the threshold.  

    Regards

    Sagar