TPS1653: Unusual Output Anomaly

ArTzy

Mastermind 19360 points

Part Number: TPS1653

Hello Experts,

I am a hardware design engineer using the TPS16530RGER in a power delivery function in a product line. The design is in the late development stage. I have a second revision hardware PCB assembly prototype that is experiencing an unusual anomaly. See the schematic below for our specific circuit implementation. Basically, transient analysis of all pins/nodes on the TPS1653 are behaving as expected except one crucial parameter in one very important use case. The design uses the TPS1653 to deliver ~ +48 V to a RJ-45 connector.

When I current limit the supply voltage to VIN (Pins 1, 2) using a voltage supply and gradually increase the current manually over 5-10 seconds, the output VOUT (Pins 17, 18) works completely as expected. The hardware current limit ILIM set using R_ILIM limits at the expected current (~3 A in my configuration). However, when I do not current limit VIN gradually, effectively just turning on the power supply for a quicker VIN rise time (~100 ms to rise to +48 V on VIN), VOUT ramps linearly as expected per the DVDT external capacitor (pin 9), rises to ~23 V then suddenly decreases exponentially to ~6 V over ~100 ms, then very gradually decreases from ~ +6 V to ~ +3 V over ~1.3 s. Then the TPS1653 faults and the output shuts down completely.

In my test setup, I am outputting to an RJ-45 connector to a high-power load resistor setup. Other than the 10 uF bulk capacitor shown in the schematic diagram (on the PCB), I am not using any other external capacitance on the test loads. Most importantly, this behavior only occurs with a load resistor configuration such that the output current is greater than ~1.65 A. With an external load resulting in 1.65 A or less at +48 V, VOUT ramps normally, reaches 48 V, and everything is fine. Greater than ~1.65 A, and it will not rise all the way to 48 V and behaves as described above when VIN is “switched on” without voltage supply current limiting.

Again, during this rise and fall, all other pins on the chip behave as expected when viewed on an oscilloscope. I use the TPS1653 on 12 channels, with one TPS1653 per channel and one RJ-45 connector per channel as well. I’ve combed the TPS1653 datasheet layout guidelines, and I am following it as closely and reasonably as possible. The 4-layer stack is:

Top - Signal
Internal 1 - Ground plane
Internal 2 - Voltage planes
Bottom – Mixed: Signal (sparsely), voltage planes

Have you ever encountered anything like this? Any idea what could be causing this behavior?

Regards,
Aaron

2 months ago

0 Aaron Zeller 2 months ago

Prodigy 70 points

So does anyone from TI help out here or is this just where problems go to die?

0 Amrit Jit 2 months ago in reply to Aaron Zeller

TI__Mastermind 37881 points

Hello Aaron,

Sorry for the delay in responding.

You are seeing TPS1653 failing to start-up when you start with resistive load of 1.65A.

I believe FET is going into thermal shut down because of high power dissipation in low VDS.

Would be better if you share the VIN, VOUT, IIN and FLT waveforms.

In your system what's the actual load? You can use the PG pin to start-up the downstream load.

PG will go high when TPS1653 is fully ON.

Thanks
Amrit

0 Aaron Zeller 2 months ago in reply to Amrit Jit

Prodigy 70 points

Sorry for the delay getting back to you. Answer your questions are below:

Amrit Jit said:
In your system what's the actual load?

Not sure what you are asking here. In my test setup it is a resistive load only, no capacitance other than the 10uF on the PCB shown in the schematic. I use rather large-sized high-power resistors of various values configured in parallel to result in desired currents. When the design is put into use, the load will be various devices that we design. The TPS1653 will function as a switchable voltage supply controller and current monitor.

Amrit Jit said:
You can use the PG pin to start-up the downstream load.

This isn't useful for our application.

Amrit Jit said:
Would be better if you share the VIN, VOUT, IIN and FLT waveforms.

Below is a scope screenshot. Timescale is 200 ms/div.

Waveform 1/yellow is VOUT at 10 V/div

Waveform 2/cyan is VIN at 10 V/div

Waveform3/violet is FLT at 2 V/div

Load is 25.115 ohms (2x 50 ohm resistors in parallel). Resulting max steady state current should be ~1.862 A, but it never even gets to that.

I don't have a good way of getting you an IIN waveform as I don't have a current probe nor a differential probe to use with a shunt. Since the load is resistive only, at this time scale, ohm's law should suffice to calculate IIN, no?

0 Amrit Jit 2 months ago in reply to Aaron Zeller

TI__Mastermind 37881 points

Hi Aaron,

When you have resistive load, it starts taking current as soon as FET turns ON.

Which means high power dissipation because VDS is high.

So, device is going into thermal regulation starts current fold back.

Can you check with decreasing the output resistance and check if start-up is successful ?

Thanks

Amrit

0 Aaron Zeller 2 months ago in reply to Amrit Jit

Prodigy 70 points

Hi Amrit,

Thank you for your reply. You wrote:

Amrit Jit said:
Can you check with decreasing the output resistance and check if start-up is successful ?

If I decrease the output resistance, the current will increase. Not sure why start-up would be successful. Like I wrote above, "this behavior only occurs with a load resistor configuration such that the output current is greater than ~1.65 A. With an external load resulting in 1.65 A or less at +48 V, VOUT ramps normally, reaches 48 V, and everything is fine. Greater than ~1.65 A, and it will not rise all the way to 48 V and behaves as described above when VIN is “switched on” without voltage supply current limiting."

Rest assured, I have done extensive testing with many different load combinations that result in currents well above and well below 1.65A.

Amrit Jit said:
Which means high power dissipation because VDS is high.

I'm not sure what you mean here. Obviously, VDS is highest when the FET is deactivated. Once it's activated, there is a very short period where the FET isn't completely on and the junction will have more resistance (I didn't look at the turn-on time in the datasheet, but it's a transient type of event in comparison to the timescale of the waveform I sent), but then the current should be less since the resistance is higher, no? Are you referring to the negative temperature coefficient of the FET, and so while it's cooler, the resistance is greater, so greater power dissipation and as it heats up, the resistance decreases?

0 Aaron Zeller 2 months ago in reply to Aaron Zeller

Prodigy 70 points

Also, I have the TPS1653 thermally sinked with vias leading to a very large internal ground plane. TPS1653 is U211 below with 4 vias on the underside ground connection. Red is the top layer with most of the chip routing, and the ground plane is not visible, but it's effectively about 50 square inches.

0 Amrit Jit 1 month ago in reply to Aaron Zeller

TI__Mastermind 37881 points

Hi Aaron,

I meant to say decrease the load.

For FET power dissipation is high during turn on when VDS is high. If resistive load is present it starts to take current when VDS is still high which will cause power dissipation and TSD will hit.

This how eFuse behaves to protect it's SOA.

Thanks

Amrit

0 Aaron Zeller 1 month ago in reply to Amrit Jit

Prodigy 70 points

Hi Amrit,

Two questions. What do you mean by "turn on?" Is that ramp up of output current/voltage until it reaches steady state or just activation of the FET from not conducting to fully conducting?

Aaron