TPS25762-Q1: TPS25762-Q1: Troubleshooting immediate failure when USB device is connected #2

Hi Marton,

Please first check the impedance between Vin and SW1 when the TPS25762 is not on the board, as discussed in the original thread.

BR,

Ke Wang

Yes, sorry i had mistakenly written nets here I wanted to write pads (maybe I should not do late night debug sessions).
So I have 3 removed TPS ICs with shorted output which can be measured with a DMM and I have a 4th which is still on the board. 

Based on the sch you attached i don't think the Vin should be short to SW. Please removed 762 can check the impedance and other components/ soldering. Looking for your updates.

Hi Wang,

This is the first IC died on my board:

This is the second:

Sorry for the misfocused images, but I measured the IN and SW1 pins:

The third one looks to be escaped from my parts bin somehow.

This is the forth died one on the board:

after removal:

The IC after removal:

So the silicon was damaged. If you are confident on the soldering, I suggest debugging the PCB first then solder new chips on it.

BR,

Ke Wang

Yes the silicon was damaged the PCB is not shorted at all.

I am confident in my soldering, I do not have XRay but I have checked the alignment of the pads with microscope also measured the nets connected to neighborhood pads for shorts with DMM: no shorts were measureable.

Do you have any advice what to debug on the PCB?

I may start from checking the voltages on the 762 pads when 762 is not soldered.

I may start from checking the voltages on the 762 pads when 762 is not soldered.

Also check C15.

In one round I desoldered (and replaced afterwards) both C15 and C14 and the capacitance was ok. They are 50V rated 100 nF MLCCs from Würth:

https://hu.mouser.com/ProductDetail/Wurth-Elektronik/885012206095?qs=0KOYDY2FL2%2FIErXVpcsrTQ%3D%3D

I will do pad measurements with removed IC tomorrow.

I measured voltages on all pads: I have the 12V on the VIN and 2.48V on the EN/UVLO line, 0V on other lines when the IC is removed.
I also measured the BOOT caps with a capacitor meter: the 100 nF is measureable through the PCB.

Hi Matron,

Let me summary here:

1. The schematic is checked and I don't think there's any major issue that will lead to a device damage.

2. The no-chip voltage measuring test you did is showing there's no OV on any pin.

3.  The firmware I gave you can work on Rev C EVM.

4. I don't think it's a chip issue since it happens on every chip and we never heard similar fault report.

5. You are confident in soldering.

I don't know if there's any thing I can directly help you, since the rest possibility is more like a certain component is picked with a wrong value/ the PCB itself have some issue/ layout is not matching sch/ etc, and these need your effort to figure out.

A potential test plan is: carefully solder a new deice, and check after which step it's damaged. Immediately after power on? Immediately after a load is connected? After a certain load time? Recording the waveforms will also important. 

Can you also double check when you claim the device is short, you are measuring with the correct direction rather than checking the body diode? From your photos seems you checked from both direction.

BR,

Ke Wang

4. I don't think it's a chip issue since it happens on every chip and we never heard similar fault report.

See this:

 TPS25762-Q1: Troubleshooting immediate failure when USB device is connected 

I spoken with Scott and he said that he never got answer for the issue and he never managed to fix his design.

Can you also double check when you claim the device is short, you are measuring with the correct direction rather than checking the body diode? From your photos seems you checked from both direction.

The failed devices are shorted in both direction.

A potential test plan is: carefully solder a new deice, and check after which step it's damaged. Immediately after power on? Immediately after a load is connected? After a certain load time? Recording the waveforms will also important. 

As the snubber circuit parts were mentioned in Scott's topic and I realized that the SW1 snubber is not populated neither on the EVM nor on the reference design I soldered on a new device and removed SW snubber. My devices got shorted right after the VBUS tried to be enabled (or at least the issue was not present until I have tried to enable the output) and now with the removed snubber the device managed to survive the the VBUS power up attempts.

However the proper VBUS voltage did not get generated, it continuously tried to ramp up the voltage to ~330 mV and then it collapsed. I had no external load on the VBUS line.

I did measured the LDOs during this period and they all looked ok:

Then I took a scope to measure the SW1 SW2 waveforms (I did not wanted to attach the Saleae inputs as they are rated to +-10 Volts).
As soon as I tried to measure SW1 the device went to short, this time between VIN and GND. I have not yet removed the IC, but with heat camera I can see that the IC is dissipating the input current. 

Is the D revision has any improvements around the SPMS driver?

By comparing my design to the EVM and to the reference board I see two major differences:

I placed one pair of the CHF caps to the opposite side (due to space constrains):

the GND connection to the internal GND layer is poor, I have way less vias connecting to the top layer than on the reference design and the EVM.

My layer order is also might not be optimal:
The upper internal layer has a GND fill, but it got sliced by the VBUS connection:

The lower internal layer is a dedicated GND plane:

Moving the GND plane to the upper layer (to be closer to the IC) could make any improvements?

Hi Marton,

1. The E2E thread you quoted do not prove it's a device issue.

2. Thanks for checking the device failure.

3. Snubber circuit on sw1 will not cause issue if you choose the correct value.

4. May I know how you enabled the Vbus when you say " I had no external load on the VBUS line"?

5. I don't think D revision has any improvements around the SPMS driver.

6. I feel moving the GND plane to the upper layer is not the critical solution for your issue?

BR,

Ke Wang

1. The E2E thread you quoted do not prove it's a device issue.

I did not said it is a device issue. I just highlighted that Scott's fault is quite similar to my case.

3. Snubber circuit on sw1 will not cause issue if you choose the correct value.

Could you please help me selecting the optimal value?
I had two 0805 2.2 Ohms parallel plus an 50V 3.3nF X7R capacitor on SW2 and 1nF on SW1. 

The reference design has 3.3nF on both sides, with 2.2Ohm on SW1 and 1 Ohm on SW2


While the EVM has 1nF on SW1 3n3 on SW2 with 1.1 Ohm on both sides:

The datasheet recommends 1.1 Ohm and 1-3.3 nF to SW1-SW2 respectively.

4. May I know how you enabled the Vbus when you say " I had no external load on the VBUS line"?

This is what I attached to the output (5K1 pulldowns on both CC lines, no load on VBUS):

5. I don't think D revision has any improvements around the SPMS driver.

Is there any reason to buy D devices (Mouser looks to have that on stock)?

6. I feel moving the GND plane to the upper layer is not the critical solution for your issue?

I am not an expert on this field (I am a digital guy). I just trying to pinpoint something in my design what could cause the device failures by checking the differences between EVM/Reference board and my design.

Hi Marton,

Thanks for the clarification.

2.2ohm//2.2ohm(0.25W) +3.3nF are recommended for both SW1 and SW2. Snubber circuit on SW2 is mandatory.

When you use the 5.1k as Rd, it's under legacy typeC protocol so 5-V Vbus is expected. In this case, due to the spec, only one 5.1 kOhm should be applied rather than on both CC lines. If putting 5.1 k on one cc is not solving the issue, please double check csn/csp pin. recording the voltages on these pins, on cc lines and on sw1 node might be helpful.

One reason for using the newest device could be the firmware support. The patch for C silicon will not be further updated and bug fix/ new features will be implement only on the newest Rev.

BR,

Ke Wang