UCC21750-Q1: Gate-Driver FLT (Fault) Pin Malfunctioning

HI Nalin,

Yes you're right. the FLT pin shouldn't be going low when DESAT is shorted to COM. Can you please share a waveform showing RDY behavior when FLT goes low and power supplies.

Best regards,

Muiz.

Hello, Muiz

Thank you for the reply. 

We have pulled-up the RDY pin to a 5V through 1k resistance, and have also verified this (specified) 5 V power supply to be OK. We also checked to see if there was any drop in the voltage when the FLT went low but nothing was observed.

Below is a part of our Gate-Driver schematic for your reference going ahead.  

Best,

Nalin Prabhath

Hi Nalin,

Can you please send me zoomed in waveforms showing FLT, output, DESAT and input signals when the issue happens. Happen all the time with the unit or does it only happen under specific conditions? In addition, does the issue happen with a different unit or just this unit?

Best regards,

Muiz.

Hi, Muiz

I have the below waveform showing:

Green: FLT pin signal
Yellow: Output signal (Ramp is slow since there are capacitors of 0.2 uF)
Red: DESAT signal
Blue: Ignore

This happens only when DC Link Voltage rises above 250 V (specified in the question previously).

This also occurs specifically at the top-switch of 3-phase, 2-level inverter.

We verified with different gate-driver units and new ones as well, at the top-switch but the observation remained the same.

Best,

Nalin Prabhath

Hi Nalin,

Thanks for sending over the waveform. I will provide a response for you by tomorrow.

Best regards,

Muiz.

Hi Muiz

Thank you for the reply. I'd be glad to provide more details if/when necessary to get to a solution. 

Best,

Nalin

Hi Nalin,

The problem you're seeing is possibly due to system-level noise. You mentioned that the issue happens once the bus voltage goes above 250V even after you change the unit and the waveform you sent is quite noisy. It's very possible that high dv/dt transients are disturbing the isolation channel causing the driver to wrongfully detect a fault. Please ensure to follow the layout and schematic guidelines attached below.

 Also, are you resetting the driver after the FLT pin goes low?

Best regards,

Muiz.

UCC21750 Schematic and Layout Design Guidelines_RevA.xlsx

Hello Muiz,

Yes, the reset pin here is connected to PWM from the firmware. Once there's a fault, the FLT pin goes low for as long as the mute period. We are bypassing this FLT pin from the firmware and so the system will not turn off. The Reset pin is given continuous PWMs again so the gate-driver will reset automatically.

I was wondering if there's a way I could send my Gerber/schematic over via email for you to verify while I cross-check the guidelines you sent. 

Best,

Nalin Prabhath

Hi Nalin,

I just sent you a friendship request. Once you answer, you can share your schematic with me. 

Best regards,

Muiz Ishola.

Hi Nalin,

I'm closing this thread since we're communicating via email.

Best regards,

Muiz.

Hi Muiz,

Thank you. 

Best, 

Nalin

Hi Nalin,

No problem.

Best regards,

Muiz