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TPS5430: EMI issue in TPS5430 Buck

Part Number: TPS5430

I'm using a TPS5430 IC for 12-5V Power converter.  The issue is the circuit fails in EMI/EMC testing, at multiple points.

I'm attaching the schematic and layout below. I followed the recommended layout as much as possible. Thing is the circuit fails in Radiated EMI emissions test. 

I'm using a shielded inductor, poured ground around the buck converter and in the layers below as well.

1. Need support from the TI Experts to solve the emissions issue

2. The recommended layout in the TI datasheet has a huge switching node with a very large area is it okay? while the app note also contradicts saying the switching node should be as low possible. which one to follow?

3. should we pour ground underneath the inductor?

A couple of things that I'm thinking to do to solve this is:
1. Add bulk capacitor in the input
2. Replace ferrite bead in the input with a inductor.

 

Apart from this it would be helpful if you can help me in fixing this!
Thanks!

 

Screenshot 2025-11-10 122440.png

 

Screenshot 2025-11-07 204331.png

 

RE_EUT_30 MHz_1000 MHz 12 V 1 Graph AIS Vertical.jpg

 

  • Hi,

    In general, for good EMI layouts, it is recommended to keep the CIN capacitors close to the VIN pins and the SW node to be kept as small as possible. You can pour ground underneath the inductor as it is shielded.

    I would recommend a bulk capacitor and an inductor on your input filter. It is important to pay attention to your input filter's attenuation curve to ensure that it is sufficient for your EMI needs. This application note is handy in determining the necessary components for your input filter: https://www.ti.com/lit/an/snva489c/snva489c.pdf

    A couple more questions from my side:

    • How many layers are on this application? You generally can get better EMI results from having more layers to shield from the noisy SW node.
    • Can the location of the high frequency capacitor be flipped with the other input capacitor? It is generally favorable to have the high frequency capacitor as close to possible to the device pins as possible.

    Thank you,
    Joshua Austria

  • Hi,

    - I've placed the 10uf bulk cap just next to the VIN pin of the IC. 

    - Should I follow the recommended layout where there is a quite long trace between the switching node, catch diode, boot cap and the inductor input. Is the length itself an issue? would making the Switching node non skinny help?

    - There is 4 layers, and the PCB is single sided assembly. There is ground underneath the layers.

    - Is this more of a layout issue or can it be solved in component level, I'm unsure about the Hot loops here.

    - There is mild ringing in the switching node of 2V in the switching node when lightly loaded. I think this is normal and acceptable?

    Thanks and regards,

    Srivatsen

  • Adding to this, I'm attaching the layer plots as well.

     Layer Plots (1).pdf

  • Hi Srivatsen,

    Yes this is usually more of a layout issue. The recommended layout for this device is not very EMI focused. The best way to ensure the best possible EMI performance would be to keep the PH trace as small as possible and arrange the required units (boot capacitor, catch diode, output inductor) around it. 

    You can try and also utilize a lower profile inductor or a snubber circuit and see if this helps. Please see this article here: https://www.ti.com/document-viewer/lit/html/SSZTBC7. A note is that a snubber will increase your device's power dissipation. 

    The SW node ring is normal, but the height of the ring is likely due to the large SW node trace or suboptimal measurement techniques. I would recommend utilizing either a differential probe or the tip and barrel method to accurately get a SW node waveform measurement.

    Thank you,

    Joshua Austria

  • Hi Joshua,

    Thanks for the response, I'll change the layout to be different from the recommended one and make the PH node smaller. I'm attaching the newer component placement here. A couple of questions:

    - The PH pin of the IC, Diode is reduced to be close to the Inductor, however the drawback to this approach is that the bootstrap cap is now much farther away from the other pins and not in direct path. Can the bootstrap cap be this much away (~3mm). 

    - I can bring the boot cap to be close to the IC's SW node but the drawback of this approach is that the direct connection between the Diode's ground pin and the IC's ground in the top layer would be broken, I would have to connect the Diode D7's ground and the IC's ground through vias. Which approach to take here, should I do direct connection to ground and keep the boot cap a bit farther from switching node or connect the diode to the IC through vias and keep the boot cap closer? Both the layout combinations are attached below

    - I'm attaching the schematics as well here. 

    Thanks!

       

  • Hi,

    Keeping the diode close is ok and having the boot cap with a bit of a larger trace on SW is a necessary tradeoff to this. I believe via-ing the return of the diode would be worse EMI wise.

    Another thing that may help would be utilizing a lower profile inductor and an input filter. Please see this application note for details on this: https://www.ti.com/lit/an/snva489c/snva489c.pdf

    Thank you,

    Joshua Austria