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TPS7A94: R_FB_PG network impedance clarification

Mark Hämmerling
Prodigy 50 points
Part Number: TPS7A94


Hi TI Support,

The TPS7A94 datasheet states that I_CL will be 100% if the parallel impedance of the R_FB network is less than 12.5k (sampled during startup).

I understand that picking 12.4k for the R_FB_PG(bottom) (as recommended in the datasheet and here) does guarantee this. But for the sake of BoM consolidation, I would like to pick 10k for the bottom resistor and calculate R_FB_PG(top) accordingly.

For I_CL=100% and PG threshold=~95% I would use:

  • for V_out(nom)=1.2V: R_FB_PG(top) = 47k
  • for V_out(nom)=3.3V: R_FB_PG(top) = 147k (=100k+47k)

Question 1:

  • Would the above R_FB_PG(top) values work for the specified use-cases?

If I understand correctly, creating a correct R_FB_PG voltage divider network is not only important for correct PG pin function (which may be of no concern if the user doesn't need PG output), but is rather critical for the IC to determine the finalization of the startup procedure and hence for stable operation.

About the divider network in the EVM:

In the EVM, both resistors of the R_FB_PG network are 10k. This raised my confidence that 10k as the bottom resistance should work just fine. However, I am still puzzled by the following statement in the EVM datasheet::

"... with R3 and R7 set to 10 k, and with the programmable current limit set to 100% of ILIMIT, the PG pin goes up when the output voltage reaches 50% of the targeted value."

Following the formula in the IC datasheet, picking 10k for both resistors with V_out(nom)=3.3V should result in a PG threshold of ~12.1%×V_out(nom).

So, question 2:

  • Can you please explain the EVM datasheet statement, or is this a typo?

Thank you very much for your help!

Best regards,
Mark

  • 0
    TI__Mastermind 37185 points

    Hi Mark,

    The EVM was finished before the values in the datasheet were finalized, which is normally not a problem, but in this instance the 10k recommendation during design shifted to 12.4k.  That's the discrepancy.  The FB_PG pin (1) also sets the current limit and (2) the threshold where fast charge (during turn on) moves over to steady state reference current.  

    Regarding (1): We assessed that the 10k resistors would still be fine for 100% current limit setting, so these were not changed in the EVM.  I did another review on the internal design and I think your resistors (10k, 47k, 147k) may work, however we cannot guarantee anything outside of the datasheet.  We still recommend the 12.4k resistor starting point.  We recommend obtaining an EVM and testing these values for yourself to confirm that the operation meets your needs.


    Regarding (2): I can now see that "target value" is ambiguous and it needs to be updated to be more clear.  Here is the operation: Using these 10k resistors, the power good will toggle when Vout = 0.4V during turn on.  There is an internal 0.2V reference which is being compared against the PG_FB pin voltage.  

    FYI: The published PSpice model predicts turn on very well for the TPS7A94/6, so feel free to use that to clarify any turn on related questions for item (2).

    Thanks,

    Stephen